Mitch Bailey
11/12/2023, 5:45 AMverilog/rtl/user_project_wrapper.v
// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
inout [`MPRJ_IO_PADS-10:0] analog_io,
So analog_io[0]
, io_out[7]
, io_in[7]
all connect to the same gpio.samarth jain
11/12/2023, 5:50 AMDinesh A
11/12/2023, 7:08 AMMitch Bailey
11/12/2023, 7:43 AMcaravel/verilog/rtl/gpio_control_block.v
and verilog/rtl/user_defines.v
Dinesh A
11/12/2023, 9:32 AM