Lab Lecture
11/10/2023, 12:44 PMMitch Bailey
11/10/2023, 3:12 PMFP_PDN_MACRO_HOOKS
syntax in json is a bit tricky. You need a ,
before and after the closing "
. If you want to share your config.json
file, we can check.Lab Lecture
11/10/2023, 3:20 PMMitch Bailey
11/10/2023, 3:42 PMgf180mcu
only has vdd
and vss
.Lab Lecture
11/10/2023, 4:19 PMMitch Bailey
11/10/2023, 4:32 PMLab Lecture
11/11/2023, 6:46 AMMitch Bailey
11/11/2023, 7:18 AMLab Lecture
11/11/2023, 7:32 AMMitch Bailey
11/11/2023, 7:33 AMconfig.json
files?Lab Lecture
11/11/2023, 8:58 AMLab Lecture
11/11/2023, 9:30 AMMitch Bailey
11/11/2023, 9:57 AMVERILOG_FILES_BLACKBOX
. It’s a hard macro so you don’t want to synthesis it - just route to it.
2. Maybe related to 1. above, but there’s no verilog sram module definition. That’s probably why you’re getting the no vdd
, vss
error. Hopefully, adding the file above will fix this error, but you’ll need to undo this
To get rid of the above error I removed VDD/VSS ports from instantiation in the user_project_wrapper.v.and put the
VDD
and VSS
connections back in.
gf180mcu_fd_ip_sram__sram512x8m8wm1 memLword0 (
.VDD(vdd),
.VSS(vss),
.CLK(clk),
.A(adr_mem0),
.D(memdatout0[7:0]),
.Q(memdatin0[7:0]),
.GWEN(memrwb0),
.CEN(memenb0),
.WEN({8{cpuen0}})
);
3. How many hard macros do you have? FP_PDN_MACRO_HOOKS
defines 4 - 2 srams, cpu
and mprj
. If you’re not using mprj
you should delete that one.
4. Add the verilog for cpu
to VERILOG_FILES_BLACKBOX
. Should look something like this
"VERILOG_FILES_BLACKBOX": [
"dir::../../verilog/rtl/cpu.v",
"pdk_dir::libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram512x8m8wm1.v"
],
Lab Lecture
11/11/2023, 10:34 AMMitch Bailey
11/11/2023, 10:46 AMcaravel_core
uses an sram macro. Looks they’ve added a wrapper. The config file is tcl, but you should be able to do the same thing in json.
https://github.com/efabless/caravel-gf180mcu/blob/main/openlane/caravel_core/config.tcl
Does your cpu.v rtl use the USE_POWER_PINS
ifdefs? Does you cpu/config.json have "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
?Lab Lecture
11/11/2023, 11:29 AMUSE_POWER_PINS
- YES
Does you cpu/config.json have "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
? - NOMitch Bailey
11/11/2023, 11:37 AMcpu/config.json
and see if it creates a gl verilog netlist with power?Lab Lecture
11/11/2023, 12:07 PMLab Lecture
11/12/2023, 2:26 PMMitch Bailey
11/12/2023, 2:46 PMconfig.json
files?Lab Lecture
11/12/2023, 6:29 PM