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Getting [ERROR PSM-0042] Unable to connect macro I...
# gf180mcu
l
Getting [ERROR PSM-0042] Unable to connect macro Instance to the power grid. Is there any change in the syntax of FP_PDN_HOOKS in config.json
m
The 
FP_PDN_MACRO_HOOKS
syntax in json is a bit tricky. You need a 
,
before and after the closing 
"
. If you want to share your 
config.json
file, we can check.
l
Last time you shared the syntax. That is working for sky130 caeavel. For gf180 is there any changes?
m
The power names are different. 
gf180mcu
only has 
vdd
and 
vss
.
l
After carefully debugging, it appears that the error is because memories cannot be connected to power. I am using sram in user_project_wrapper.
m
There have been some slack discussions about being unable to connect power to sram. Is the top metal on the sram macro metal3? If it is, you might need to modify the power connection script.
l
I see. The error comes at the IR drop analysis script.
m
@Lab Lecture do you need more assistance with this?
l
Yes. How to resolve this issue.
m
Can you share your 
config.json
files?
l
First, @Mitch Bailey thanks for for offerring help. There are few issues. SRAM instantiation issue. This is the definition of the SRAM I am using * Data Created: 05-06-2014 * Revision: 0.0 * * Description: gf180mcu_fd_ip_sram__sram512x8m8wm1 Simulation Model */ `timescale 1 ps / 1 ps module gf180mcu_fd_ip_sram__sram512x8m8wm1 ( CLK, CEN, GWEN, WEN, A, D, Q, VDD, VSS ); I am using it in user_project_wrapper.v as below gf180mcu_fd_ip_sram__sram512x8m8wm1 memLword0 ( .VDD(vdd), .VSS(vss), .CLK(clk), .A(adr_mem0), .D(memdatout0[7:0]), .Q(memdatin0[7:0]), .GWEN(memrwb0), .CEN(memenb0), .WEN({8{cpuen0}}) ); I am getting error at STEP 1 as below 8.1. Analyzing design hierarchy.. ERROR: Module `gf180mcu_fd_ip_sram__sram512x8m8wm1' referenced in module `user_project_wrapper' in cell `memLword0' does not have a port named 'VSS'. child process exited abnormally [ERROR]: Creating issue reproducible... That means the SRAM lib/lef/def/gds does not have power pins.
"PL_RANDOM_GLB_PLACEMENT": 1, "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0, "PL_RESIZER_TIMING_OPTIMIZATIONS": 0, "GLB_RESIZER_DESIGN_OPTIMIZATIONS": 0, "GLB_RESIZER_TIMING_OPTIMIZATIONS": 0, "PL_RESIZER_BUFFER_INPUT_PORTS": 0, "FP_PDN_ENABLE_RAILS": 0, "GRT_REPAIR_ANTENNAS": 0, "DIODE_INSERTION_STRATEGY": 0, "DIODE_ON_PORTS": "None", "RUN_HEURISTIC_DIODE_INSERTION": 0, "RUN_FILL_INSERTION": 0, "RUN_TAP_DECAP_INSERTION": 0, "RUN_CTS": 0, "MAGIC_ZEROIZE_ORIGIN": 0, "FP_SIZING": "absolute", "DIE_AREA": "0 0 2980.2 2980.2", "CORE_AREA": "12 12 2968.2 2968.2", "RUN_CVC": 0, "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", "UNIT": 2.4, To get rid of the above error I removed VDD/VSS ports from instantiation in the user_project_wrapper.v. gf180mcu_fd_ip_sram__sram512x8m8wm1 memLword0 ( .CLK(clk), .A(adr_mem0), .D(memdatout0[7:0]), .Q(memdatin0[7:0]), .GWEN(memrwb0), .CEN(memenb0), .WEN({8{cpuen0}}) ); Then I get the following Error [STEP 21] [INFO]: Creating IR Drop Report (log: ../home/aloke/projects/caravel_user_project/openlane/user_project_wrapper/runs/23_11_11_14_31/logs/signoff/21-irdrop.log)... [WARNING]: VSRC_LOC_FILES is not defined. The IR drop analysis will run, but the values may be inaccurate. [ERROR]: during executing openroad script /openlane/scripts/openroad/irdrop.tcl [ERROR]: Log: ../home/aloke/projects/caravel_user_project/openlane/user_project_wrapper/runs/23_11_11_14_31/logs/signoff/21-irdrop.log [ERROR]: Last 10 lines: [INFO]: Setting timing derate to: 5.0 % [INFO]: Setting clock latency range: 4.65 : 5.57 [INFO]: Setting clock transition: 0.61 [INFO]: Setting RC values... [INFO PSM-0022] Using 5.000V for vdd [INFO PSM-0076] Setting metal node density to be standard cell height times 5. [INFO PSM-0031] Number of PDN nodes on net vdd = 1746. [ERROR PSM-0042] Unable to connect macro/pad Instance memHword0 to the power grid. Error: irdrop.tcl, 35 PSM-0042 child process exited abnormally My config.json is: { "PDK": "gf180mcuD", "DESIGN_NAME": "user_project_wrapper", "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", "VERILOG_FILES": [ "dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v" ], "CLOCK_PORT": "user_clock2", "CLOCK_NET": "mprj.soc_clk", "CLOCK_PERIOD": 25, "MACRO_PLACEMENT_CFG": "dir::macro.cfg", "VERILOG_FILES_BLACKBOX": [ ], "EXTRA_LEFS": [ "dir::../../lef/cpu.lef", "dir::../../dependencies/pdks/gf180mcuD/libs.ref/gf180mcu_fd_ip_sram/lef/gf180mcu_fd_ip_sram__sram512x8m8wm1.lef" ], "EXTRA_GDS_FILES": [ "dir::../../gds/cpu.gds", "dir::../../dependencies/pdks/gf180mcuD/libs.ref/gf180mcu_fd_ip_sram/gds/gf180mcu_fd_ip_sram__sram512x8m8wm1.gds" ], "EXTRA_LIBS": [ "dir::../../lib/cpu.lib", "dir::../../dependencies/pdks/gf180mcuD/libs.ref/gf180mcu_fd_ip_sram/liberty/gf180mcu_fd_ip_sram__sram512x8m8wm1__tt_025C_5v00.lib" ], "EXTRA_SPEFS": [ "cpu", "dir::../../spef/multicorner/cpu.min.spef", "dir::../../spef/multicorner/cpu.nom.spef", "dir::../../spef/multicorner/cpu.max.spef", ], "FP_PDN_MACRO_HOOKS": [ "mprj vdd vss vdd vss,", "cpu0 vdd vss vdd vss,", "memLword0 vdd vss vdd vss,", "memHword0 vdd vss vdd vss" ], "QUIT_ON_SYNTH_CHECKS": 0, "FP_PDN_CHECK_NODES": 0, "SYNTH_ELABORATE_ONLY": 1, "PL_RANDOM_GLB_PLACEMENT": 1, "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0, "PL_RESIZER_TIMING_OPTIMIZATIONS": 0, "GLB_RESIZER_DESIGN_OPTIMIZATIONS": 0, "GLB_RESIZER_TIMING_OPTIMIZATIONS": 0, "PL_RESIZER_BUFFER_INPUT_PORTS": 0, "FP_PDN_ENABLE_RAILS": 0, "GRT_REPAIR_ANTENNAS": 0, "DIODE_INSERTION_STRATEGY": 0, "DIODE_ON_PORTS": "None", "RUN_HEURISTIC_DIODE_INSERTION": 0, "RUN_FILL_INSERTION": 0, "RUN_TAP_DECAP_INSERTION": 0, "RUN_CTS": 0, "MAGIC_ZEROIZE_ORIGIN": 0, "FP_SIZING": "absolute", "DIE_AREA": "0 0 2980.2 2980.2", "CORE_AREA": "12 12 2968.2 2968.2", "RUN_CVC": 0, "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", "UNIT": 2.4, "FP_IO_VEXTEND": "expr::2 * $UNIT", "FP_IO_HEXTEND": "expr::2 * $UNIT", "FP_IO_VLENGTH": "expr::$UNIT", "FP_IO_HLENGTH": "expr::$UNIT", "FP_IO_VTHICKNESS_MULT": 4, "FP_IO_HTHICKNESS_MULT": 4, "FP_PDN_CORE_RING": 1, "FP_PDN_CORE_RING_VWIDTH": 3.1, "FP_PDN_CORE_RING_HWIDTH": 3.1, "FP_PDN_CORE_RING_VOFFSET": 14, "FP_PDN_CORE_RING_HOFFSET": 16, "FP_PDN_CORE_RING_VSPACING": 1.7, "FP_PDN_CORE_RING_HSPACING": 1.7, "FP_PDN_HOFFSET": 5, "FP_PDN_HPITCH_MULT": 1, "FP_PDN_HPITCH": "expr::60 + $FP_PDN_HPITCH_MULT * 30", "FP_PDN_VWIDTH": 3.1, "FP_PDN_HWIDTH": 3.1, "FP_PDN_VSPACING": "expr::5 * $FP_PDN_CORE_RING_VWIDTH", "FP_PDN_HSPACING": 26.9, "VDD_NETS": [ "VDD_NETS": [ "vdd" ], "GND_NETS": [ "vss" ], "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS", "RUN_LINTER": 0, "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def", "BASE_SDC_FILE": "dir::base_user_project_wrapper.sdc", "SIGNOFF_SDC_FILE": "dir::signoff.sdc" }
m
Ok, let’s try a couple things. 1. Add the sram verilog to 
VERILOG_FILES_BLACKBOX
. It’s a hard macro so you don’t want to synthesis it - just route to it. 2. Maybe related to 1. above, but there’s no verilog sram module definition. That’s probably why you’re getting the no 
vdd
, 
vss
error. Hopefully, adding the file above will fix this error, but you’ll need to undo this
To get rid of the above error I removed VDD/VSS ports from instantiation in the user_project_wrapper.v.
and put the 
VDD
and 
VSS
connections back in.
Copy code
gf180mcu_fd_ip_sram__sram512x8m8wm1 memLword0 (
    .VDD(vdd),
    .VSS(vss),
    .CLK(clk),
    .A(adr_mem0),
    .D(memdatout0[7:0]),
    .Q(memdatin0[7:0]),
    .GWEN(memrwb0),
    .CEN(memenb0),
    .WEN({8{cpuen0}})
);
3. How many hard macros do you have? 
FP_PDN_MACRO_HOOKS
defines 4 - 2 srams, 
cpu
and 
mprj
. If you’re not using 
mprj
you should delete that one. 4. Add the verilog for 
cpu
to 
VERILOG_FILES_BLACKBOX
. Should look something like this
Copy code
"VERILOG_FILES_BLACKBOX": [
            "dir::../../verilog/rtl/cpu.v",
            "pdk_dir::libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram512x8m8wm1.v"
        ],
l
The problem with Verilog_files_blackbox is that it want gl/*.v in the latest gf180-1b. And sram doesn't have a gate level netlist. If I use a RTL .v file (for any macro) openlane complains and error out. That is why I did not use anything in verilog_files_blackbox My design cpu.v also has power ports and i have hardened it using openlane. So verilog/gl/cpu.v is generated. But there the power ports are missing. So I can't use power ports in instigation of my own macros even
m
Sorry for the bad advice. The 
caravel_core
uses an sram macro. Looks they’ve added a wrapper. The config file is tcl, but you should be able to do the same thing in json. https://github.com/efabless/caravel-gf180mcu/blob/main/openlane/caravel_core/config.tcl Does your cpu.v rtl use the 
USE_POWER_PINS
ifdefs? Does you cpu/config.json have 
"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
?
l
Does your cpu.v rtl use the 
USE_POWER_PINS
- YES Does you cpu/config.json have 
"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
? - NO
m
Can you add that to 
cpu/config.json
and see if it creates a gl verilog netlist with power?
l
Will make all the changes and run again. SRAM - looks like I am able to understand what needs to be done.
👍 1
Just to update and complete the thread, I could not solve the sram power connection issue. I could not create the wrapper. Still thanks for the help.
m
Thanks for the update. Do you want to continue to work on the problem? If so, could you share all your 
config.json
files?
l
I will send. BTW, the whole design is taped out of sky130A without any issues. With 1k sram.
👍 1
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