All of those DRCs are from Openlane's `TOP_digital...
# shuttle-prechecke
Ellen Wood
11/09/2023, 10:45 AMAll of those DRCs are from Openlane's
TOP_digitald
Dinesh A
11/09/2023, 12:39 PMTop-level routing will use macro's .lef to find the metal blockage info. Based on these details tool route around the Macros.
When you re-route the macro, then blockage/free space information will change. This may result in DRC around the macro's.
You need to re-route the top-level with latest macro's .lef details
e
Ellen Wood
11/09/2023, 2:24 PMI don't think the problem comes from the routing. All of the errors are within the digital circuitry contained inside the digital Macro which Openlane makes
Ellen Wood
11/09/2023, 2:24 PMimage.png
Ellen Wood
11/09/2023, 2:24 PMI gave it no LEFs to make this. Just verilog
d
Dinesh A
11/09/2023, 2:49 PMYou may be using older drc rule for hardening the macro then the pre-check drc file.
You can cross-check your local PDK drc file: $PDK_ROOT/$PDK/libs.tech/klayout/drc/sky130A_mr.drc
Vs drc file in precheck folder: open_mpw_precheck/checks/tech-files/sky130A_mr.drc
Dinesh A
11/09/2023, 2:50 PMTop-level integration takes three information for each macros : verilog, .lef and .gds
You can cross-check your top-level config.tcl
Verilog will be listed under: set ::env(VERILOG_FILES_BLACKBOX)
LEF will be listed under set ::env(EXTRA_LEFS)
GDS will be listed under set ::env(EXTRA_GDS_FILES)
e
Ellen Wood
11/09/2023, 2:53 PMI'll double check the PDKs are up to date, but I did clone a brand new mpw-9f repo yesterday and ran make setup. So I imagine they are as current as they can be. Our TOP level is this:
Ellen Wood
11/09/2023, 2:53 PMimage.png
Ellen Wood
11/09/2023, 2:53 PMTOP_mixed
Ellen Wood
11/09/2023, 2:53 PMWe gave user_project_wrapper LEF and GDS for this. But TOP_digital is just a cell placed in there, which was separately hardened in Openlane (make TOP_digital)
Ellen Wood
11/09/2023, 3:04 PMAnd its that previously hardened TOP_digital cell that contains most of the FEOL errors!
m
Marwan Abbas
11/11/2023, 3:53 PM@Ellen Wood what are the std cells causing the issues? you can decrease the hierarchy in klayout and get the std cell names that have errors.
e
Ellen Wood
11/13/2023, 10:48 AM@Marwan Abbas the problem was solved by instantiating the .gds which openlane generated into Magic, instead of the .mag file which Openlane made. The errors were actually getting created by Magic when writing the .mag file to GDS. 🙂
m
Marwan Abbas
11/13/2023, 10:50 AMCan you please create an issue on openlane if you haven't already?