In gfmpw-1b branch, for user_project_wrapper config.json, the VERILOG_FILES_BLACKBOX needs files from dir:../.../verilog/gl/..... Means, gate level netlist. Is it intended? For sky130 black box files from verilog/rtl/... are required

@Lab Lecture Since they’re black boxed, it may not make a difference.

Looks like it does matter. Macro instanciation is checked with macro definition. Port mismatch is checked. For example, we define power ports in each macro to connect to the power ports defined in user_project_wrapper.v. In the verilog/gl/* netlists the power ports are removed. So openlane errors out.

@Lab Lecture power ports are in some gl netlists and not others. Powered gate level netlists are necessary for LVS. The ones with power would probably work for black-boxes.