Does the extraction of parasitic capacitances take into account the increase in capacitance by the metal fill? It seems to me the metal fill can substantially alter the extracted capacitances. Given the large fill in M1 to M3 the capacitances might be increased by almost 50% for the upper metal layers due to the fill. Is the fact that metal fill will be added taken into account? For example: Between M2 and M4 there is M3. If there is no metal on M3, but a delectric, the dielectric thickness between M2 and M4 is 1.65µm. If there is metal on M3, the dielectric thickness is reduced to 0.8 µm. This is substantial!

it is possible to run the fill generation algorithm manually and then extract. I usually don't do so because it creates a ton of floating caps that slow down the simulation. But I agree, it's a good idea to check what the difference is, and necessary if you want an accurate result.

Thank you! I think I know what I'd have to do. I fear simulation times will explode. Already without the caps from the fill, the extracted spice files take forever to simulate.

@Tim Edwards how do you run the fill generation manually?

@Tom:

$PDK_ROOT/sky130A/libs.tech/magic/generate_fill.py

. However, there is a version of this that is in, I think, the

mpw_precheck

repository that's a bit more flexible and has an option flag to take a GDS file as input instead of a .mag file. The output is a GDS file with just the fill which can then be overlaid on the original layout before extraction, in the use case being mentioned in this thread.

Thanks, @Tim Edwards. I actually ment for GF180mcu. I don't see an equivalent in there at the same path.

Oh. I never developed a fill generation script for GF180MCU because Global Foundries would run fill generation themselves. But that definitely messes up the ability to check the effect of fill on parasitic extraction.