Hello All, I have a couple of ring oscillator cells that have a height of 8.8um that I am attempting to include in the openlane flow as individual cells that ultimately interface with a mux16x1 design synthesized and PNR'ed inside of the openlane flow using the

sky130_fd_sc_hd

standard cell library. I have successfully gotten through detail and global routing but I have hit a snag on the

PDN

settings as I get this error on

STEP 22

of the openlane flow:

[ERROR]: during executing openroad script /openlane/scripts/openroad/irdrop.tcl
[ERROR]: Log: ../import/yukari1/lrburle/google_ring_oscillator/caravel/openlane/user_project_wrapper/runs/23_11_06_09_58/logs/signoff/22-irdrop.log
[ERROR]: Last 10 lines:
Reading design constraints file at '/import/yukari1/lrburle/google_ring_oscillator/caravel/openlane/user_project_wrapper/runs/23_11_06_09_58/tmp/floorplan/3-initial_fp.sdc'���
[INFO]: Setting RC values...
[INFO PSM-0001] Reading voltage source file: /import/yukari1/lrburle/google_ring_oscillator/caravel/openlane/user_project_wrapper/test.csv.
[INFO PSM-0002] Output voltage file is specified as: /import/yukari1/lrburle/google_ring_oscillator/caravel/openlane/user_project_wrapper/runs/23_11_06_09_58/reports/signoff/22-irdrop-vccd1.rpt.
[INFO PSM-0015] Reading location of VDD and VSS sources from /import/yukari1/lrburle/google_ring_oscillator/caravel/openlane/user_project_wrapper/test.csv.
[INFO PSM-0076] Setting metal node density to be standard cell height times 5.
[INFO PSM-0031] Number of PDN nodes on net vccd1 = 843.
[ERROR PSM-0042] Unable to connect macro/pad Instance ro1 to the power grid.
Error: irdrop.tcl, 35 PSM-0042
child process exited abnormally

[ERROR]: Creating issue reproducible...

Where ro1 is a ring-oscillator instance that I instantiated in the

rtl

directory. Here are some of my

config.json

settings found in the

user_project_wrapper

directory:

"DESIGN_IS_CORE": 1,
    "FP_PDN_CORE_RING": 1,
    "VDD_NETS": [
        "vccd1"
    ],
    "GND_NETS": [
        "vssd1"
    ],
    "FP_PDN_CORE_RING_VWIDTH": 3,
    "FP_PDN_CORE_RING_HWIDTH": 3,
    "FP_PDN_CORE_RING_VOFFSET": 14,
    "FP_PDN_CORE_RING_HOFFSET": 14,
    "FP_PDN_CORE_RING_VSPACING": 1.7,
    "FP_PDN_CORE_RING_HSPACING": 1.7,
    "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
    "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
    "FP_PDN_VWIDTH": 3,
    "FP_PDN_HWIDTH": 3,
    "FP_PDN_VOFFSET": 0,
    "FP_PDN_HOFFSET": 0,
    "FP_PDN_VPITCH": 186,
    "FP_PDN_HPITCH": 186,

I have been trying to follow the document found here but I haven't had any luck. Anyone happen to know how to configure the PDN settings correctly for this scenario? Thanks in advance!

@Landon Burleson the only thing that might be missing is if your macro power names are not

vccd1/vssd1

. If they are not the same, you probably want to add

FP_PDN_MACRO_HOOKS

. This probably requires

"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",