@Ellen Wood: Try drawing layer "pwell" under the nFETs, connecting both the transistor and the tap. The "pwell" is not a physical mask layer, but it should help magic figure out that there's a pwell in the middle of the deep nwell structure.

@Tim Edwards please correct me if I’m wrong, but pwell is not a gds layer, is it? precheck LVS uses gds as input.

@Mitch Bailey: Yes, you're right. That wouldn't help. I'd have to look at the layout, then. I've done plenty of deep nwell structures and they extract fine; the cifinput rules reconstruct the pwell under the nFET devices when the GDS is read. I'm not sure what's different about this situation.

Hi @Mitch Bailey our last 'true' pre-tapeout issue (LVS + DRC) is something to do with this Deep N well. I'm getting a Klayout FEOL error associated with it. From the Layer Pallet in Klayout, it doesn't look like the Deep N Well has extracted from Magic correctly? This is probably why its causing the LVS error with the floating net/port. There's no DRCs in Magic itself. I can send you the .mag files or upload them to the Efabless website - really need urgent help with this please! As its the last proper problem before tonights Tape out!! 😞

@Ellen Wood Do you understand the drc error? The nwell guard ring must overlap and be overlapped by deep nwell. The right side of the deep nwell is flush with the nwell guard ring.

No I did not understand that!

Extending should be ok, the cross section needs to look like this so that the pwell is totally isolated from the psubstrate. If the deep nwell does not overlap nwell on all sides, pwell will connect to the underlying psubstrate.

======-----------======
| NW |     PW    | NW |
===~~~~~~~~~~~~~~~~~===
PS |     DNW       | PS
   ~~~~~~~~~~~~~~~~~