Hello, a further Magic related LVS question. Magic seems to be recognising a large piece of Deep N Well as a parasitic device. All of the cells in the hierarchy that reference the cell containing the Deep N Well have an added subcircuit pin in their subcircuit definitions in

user_project_wrapper.gds.spice.

In both layout and schematic, the net associated with the Deep N Well is labelled (

TXRX_B_POS_via_R

), but not ported out, so the .spice file from Xschem doesn't show it. Therefore we have LVS mismatches because every cell in the Layout has one extra pin in their pin list than in reality. The behavior is similar to what we've seen when the parasitic extraction is on in Magic. Is there any way to stop this happening please? 🙂

@Ellen Wood magic extracts the circuit hierarchically. If you have deep nwell split between cells you might get unexpected results. deep nwell must be enclosed by an nwell guard ring. If your guard ring is split between cells, you’ll also get unexpected results. The easiest way to extract the circuit correctly might be to list all your cells with deep nwell in the

EXTRACT_FLATGLOB

section of the

lvs_config.json

file. Note: it requires that you also flatten all their subcells too. The openRAM sram layouts add the deep nwell and gaurdrings at the top hierarchy, so that’s another way to do it.

Thanks for you advise Mitch, we only have 1 cell containing a deep N well in the layout, and neither the N well nor the guard ring are split between any cells. I have sent the layout files to Tim to have a look. I will also try using the EXTRACT_FLATGLOB option as you mentioned.