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Is there a full checklist specifically for analog ...
# chipignite
l
Is there a full checklist specifically for analog projects somewhere?
t
Harald Pretl has the best understanding of this, followed by me, I suppose. We are all pretty busy at the moment preparing things for the upcoming tapeout. There are several different ways of going about an analog project, all of which are technically valid, and have their own pros and cons. One is to hand-design the analog block and manually connect it up to the wrapper pins; the other is to make the analog into a macro and use openlane to assemble it into the wrapper. At the end of the day, what you submit is a GDS file that matches the project wrapper layout. The details are in running DRC, LVS, extraction, and simulations. Where are you in that process?
l
I am still very early in the process -- only found about this shuttle on thursday. I'm trying to build https://gitlab.com/carllb52/mixed-signal-reram-mpw7-2 but going through some config errors. (Currently on the "No rule to make target 'mprj_por.hex', needed by 'mprj_por.vvp'" thing which seems there's already a tip for in the slack)
How do I google for "macro"?
e
image.png
👍 1
This has been our approach. Top level mixed signal = 
TOP_mixed
. Digital: Simulation with verilog test bench and GTKwave etc. Harden verilog into 
TOP_digital
, using Openlane in the standard way from caravel_user_project directory: (
make TOP_digital)
. Instantate this as a cell in Magic. Copy its Ports up to the top level (and move those on the bottom down to the very edge of the bounding box so Openlane can reach it during routing). Analog: hand drawn (magic), LVS/simulation (xschem, netgen). Top level analog = 
TOP_analog
, instantated as a cell in Magic. Top level hand edits: • Digital + Analog cells hand wired together. • Analog connections to the GPIOs hand drawn and turned into ports for Openlane to reach • M4 power rails drawn and turned into ports (
vccd1
and 
vssd1
) so Analog macro will be powered - update the FP_PDN_MACRO_HOOKS line in user_project_wrapper 
config.json
Export GDS and LEF (
lef write -hide
) from TOP_mixed in Magic, put these into the correct directory (/gds and /lef). Edit 
user_project_wrapper.v
to describe all the connections for routing to TOP_mixed ports. Harden TOP_mixed in Openlane (
make user_project_wrapper
) Run pre-check - providing gate level verilog files for the digital and TOP_mixed, and a spice netlist for TOP_analog
🙌 1
✅ 1
Seems to be working ok so far, still a few final bits to do on LVS and Klayout DRCs
l
Really appreciate this info, thank you
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