Hello, I am trying to submit a project and I'm getting lvs errors that I cannot explain. Particularly, vccd1 is not matching vccd1 for modules that are smaller than ~200 x 200 um.

...
wbs_stb_i                                  |wbs_stb_i                                  
wbs_we_i                                   |wbs_we_i                                   
(no matching pin)                          |vccd1                                      
vccd1                                      |(no matching pin)     
---------------------------------------------------------------------------------------
Cell pin lists for user_project_wrapper and user_project_wrapper altered to match.
Device classes user_project_wrapper and user_project_wrapper are equivalent.

Final result: Top level cell failed pin matching.

This seems to happen when my module gets the power grid altered.

[WARNING]: Current core area is too small for the power grid settings chosen. The power grid will be scaled down.

This should be fine with my current design as it is literally a single mux to control what clock signal is fed into my main module.