I've created a simple circuit using custom capacitors and MOSFET. However, during the extraction process in Magic for LVS, I noticed that the part defining the connections of the capacitors was not extracted. Can you help me identify what the problem might be?

Looks like you’re making a lateral metal capacitor. These devices are not extractable with the current tech file. There is no recognition layer and thus no way to distinguish between a capacitor and 2 parallel wires.

So, does that mean if I want to create and use a custom capacitor, it's technically not possible to run LVS?

I think if you create a custom device you also need to provide LVS rules to recognize this device on the layout. In some cases this requires as @Mitch Bailey said a recognition layer if this device can not be uniquely be identified by its own layers. This is for example the case of metal resistors, where a piece of metal line is usually considered a conductor joining devices together. If such a line is to be considered a (small valued) resistor a dedicated layer is used.

You can do a partial lvs by ignoring

hgu_cdac_unit

.

@정진형학부생: If it's a device, then it needs a device model. The best thing to do here would be to run a parasitic extraction on just the device layout to get the capacitance value of the device, then create a subcircuit model that defines

hgu_cdac_unit

and instantiates one capacitor of the correct value (preferably with a substrate connection and other parasitic caps from the cap terminals to substrate). Then, in your

hgu_cdac_unit

layout, create a property

property device primitive

and make sure that the device layout has ports, and that the port indexes match the order of ports in the defined subcircuit. If you have capacitors in parallel, then you will need to make your own copy of the netgen LVS setup file and add your device to the list of capacitors, so that it will know how to add the devices in parallel.

Thank you. I decided to treat the custom cap_unit as a black box and ignore it when running LVS. During this process, there seems to be one issue that I'm encountering. I'm getting the "Property errors were found" when running LVS, along with "Circuits match uniquely". but I don't understand the meaning of this error. If a match uniquely, is it possible to ignore this error? Can you please let me know under what circumstances this error occurs? The file used for LVS is located below.

What command are you using for extraction and LVS? It looks like magic may be extracting two layout cells exactly on top of each other as 2 devices.

I used the following command in Magic. The cthresh value was set to 0.

I can't tell a whole lot without looking at the layout, but from the netlist, there are two devices in this cell:

.subckt sky130_fd_pr__nfet_01v8_MVW3GX a_63_n42# a_n125_n42# a_33_n68# a_n81_n130#
+ a_n33_n42# VSUBS
X0 a_63_n42# a_33_n68# a_n33_n42# VSUBS sky130_fd_pr__nfet_01v8 ad=0.13 pd=1.46 as=0.0693 ps=0.75 w=0.42 l=0.15
X1 a_n33_n42# a_n81_n130# a_n125_n42# VSUBS sky130_fd_pr__nfet_01v8 ad=0.0693 pd=0.75 as=0.13 ps=1.46 w=0.42 l=0.15
.ends

And according to the pin connections, they have been connected in parallel:

Xsky130_fd_pr__nfet_01v8_MVW3GX_0 m1_15709_1421# m1_15709_1421# OUT OUT VDD VSS sky130_fd_pr__nfet_01v8_MVW3GX

which would result in a total width of 0.42 + 0.42 = 0.84. In the schematic view, there is only one device here with width 0.42.

Thank you for your response! After debugging, I found that using the mosfet of the nf model caused the finger to be ignored, resulting in this issue due to a change in the size of the mosfet. By using the mosfet of the normal model to modify the finger and writing the W value as total W, the problem was resolved. Your response was very helpful. (Reference Slack response: https://open-source-silicon.slack.com/archives/C032Y8J3KHA/p1660669455911239?thread_ts=1660667362.613069&cid=C032Y8J3KHA)