Regarding Klayout FEOL and BEOL DRC violations on ...
# chipignite
e
Regarding Klayout FEOL and BEOL DRC violations on the pre-check, where is the best place to correct these? Directly in the user_project_wrapper.gds which Openlane generates, or in the .gds of the Macro we are feeding to Openlane to build (or does it not really matter?)
j
Hi Ellen - what are the errors? generally openlane should not be generating DRC errors.
e
Hi @jeffdi - the errors in the Openlane-generated Macro are npc.2, nsd.2, and psd.2
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Its generated 13 of them in total in our digital macro
hi @jeffdi - we are still being troubled by DRCs generated by Openlane in the digital circuitry. Its making passing the pre-check really difficult because they keep popping up in different combinations
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