Hello, running the pre-check locally on our full Analog macro now. Getting hundreds of these errors - is there any way to tell Magic to merge the transistors in the layout on extraction?

@Ellen Wood Currently, it looks like magic is extracting your

transistor…PFET

gates as unconnected. magic works best if there are ports at each level of the hierarchy. You can try flattening these cells before extraction by adding the cell names to

EXTRACT_FLATGLOB

in your

lvs_config.json

file.

Thank you - I think I will try adding ports to each level of hierarchy - shouldn't take too long.