< Mitch Bailey> I am facing FEOL BEOL errors in local preche open-source-silicon.dev #shuttle-precheck

<@U017X0NM2E7> I am facing FEOL , BEOL errors in l...

vks

11/04/2023, 8:09 AM

@Mitch Bailey I am facing FEOL , BEOL errors in local precheck and trying to rectify them. Is there any way in local precheck to run only these specific checks and skip other checks in order to save time.

Mitch Bailey

11/04/2023, 8:45 AM

@vks I think you’d have to add a new target to

caravel_user_project/Makefile

. Something like this might work for just the klayout feol and beol.

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run-precheck-drc: check-pdk check-precheck
        $(eval INPUT_DIRECTORY := $(shell pwd)) \
        cd $(PRECHECK_ROOT) && \
        docker run -it -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
        -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
        -v $(PDK_ROOT):$(PDK_ROOT) \
        -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \
        -e PDK_PATH=$(PDK_ROOT)/$(PDK) \
        -e PDK_ROOT=$(PDK_ROOT) \
        -e PDKPATH=$(PDKPATH) \
        -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
        efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK) klayout_feol klayout_beol";

vks

11/04/2023, 8:50 AM

Thanks @Mitch Bailey

Mitch Bailey

11/04/2023, 9:28 AM

Remember, those have to be tabs in the Makefile.

vks

11/04/2023, 9:38 AM

Sure. Able to clear all other precheck errors only LVS is remaining. Standalone LVS run between .spice netlist of

user_project_analog_wrapper

layout and schematic is matching uniquely with only propoerty errors (which is fine with my design). But during local precheck getting LVS error. Please suggest what could be the issue.

lvs.log LVS_check.log precheck.log

Mitch Bailey

11/04/2023, 10:39 AM

@vks It may be a problem with the magic version on the platform. Can you share your

precheck_results/<tag>/tmp/ext.log

file?

Mitch Bailey

11/04/2023, 10:52 AM

Your precheck log shows

Open PDKs: fa9f29b3e054560cb0e5d7c94dc258dd56f413ce

but I can’t find that anywhere. Have you modified the pdk locally? Can you try with the default pdk?

vks

11/04/2023, 12:31 PM

@Mitch Bailey

ext.log

file is attached. I haven't modified pdk locally. How to try with default pdk now ?

ext.log

Mitch Bailey

11/04/2023, 1:14 PM

Can you show me the results of these commands?

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$ echo $OPEN_PDKS_COMMIT
$ grep Makefile OPEN_PDKS_COMMIT

vks

11/04/2023, 2:01 PM

Please check the output...

Mitch Bailey

11/04/2023, 2:15 PM

Sorry, 😬. What about this?

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grep OPEN_PDKS_COMMIT Makefile

vks

11/04/2023, 2:16 PM

Here's the output

Mitch Bailey

11/04/2023, 2:30 PM

Ok. Unfortunately, the version of precheck has an older magic tech file. There is an update pending, but lets try something else first. In the lvs_config.json file, can you add a

LVS_SPICE_FILES_TO_FIX

variable and move your top level spice netlist to there? If you share your

lvs_config.json

file after you make the change, I can check it.

vks

11/04/2023, 2:37 PM

Sharing updated

lvs_config.json

file as per your suggestion

lvs_config.json

vks

11/04/2023, 3:28 PM

I ran with updated

lvs_config.json

but LVS error is still there in local precheck.

Mitch Bailey

11/04/2023, 3:50 PM

@vks You’re using some devices that haven’t been incorporated into the be checks flow yet. That’s what’s causing the soft connection, CVC, and OEB check errors. Is your repo open source? If it is, I could clone it and make some changes to get precheck to run (better). I can’t tell where the problem is with LVS though. Could you resend

LVS_check.log

and

precheck_results/<tag>/tmp/lvs.report

vks

11/04/2023, 4:10 PM

Repo is not open-sourced but collaborator access provided to repo on efabless. You can please check it there.

lvs.report LVS_check.log

Mitch Bailey

11/04/2023, 4:36 PM

First, can you add

io_metal_patch_array_16x16

EXTRACT_ABSTRACT

? I’m guessing that this has no metal connections to the external circuit. This is causing a problem in the soft connection check.

Mitch Bailey

11/04/2023, 5:05 PM

@vks Can you replace the following 3 files in

$PRECHECK_ROOT/checks/be_checks/tech/

(

$PRECHECK_ROOT

defaults to

$HOME/mpw_precheck

). ==> sky130A/cvc.models <==

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MN nfet_01v8 Vth=0.2 Vgs=1.8 Vds=1.8
MP pfet_01v8_hvt Vth=-0.2 Vgs=1.8 Vds=1.8

R short model=switch_on

D sky130_fd_pr__diode_pw2nd_05v5 
D sky130_fd_pr__diode_pw2nd_11v0 
D sky130_fd_pr__diode_pw2nd_05v5_lvt
D sky130_fd_pr__diode_pw2nd_05v5_nvt 
D sky130_fd_pr__diode_pd2nw_05v5
D sky130_fd_pr__diode_pd2nw_05v5_lvt
D sky130_fd_pr__diode_pd2nw_11v0
D sky130_fd_pr__model__parasitic__diode_ps2dn
D sky130_fd_pr__model__parasitic__diode_ps2nw
D sky130_fd_pr__model__parasitic__diode_pw2dn
D condiode


#R sky130_fd_pr__res_generic_m1 R=l/w*0.125
#R sky130_fd_pr__res_generic_m2 R=l/w*0.125
#R sky130_fd_pr__res_generic_m3 R=l/w*0.047
#R sky130_fd_pr__res_generic_m4 R=l/w*0.047
#R sky130_fd_pr__res_generic_nd R=l/w*0.029
R sky130_fd_pr__res_generic_l1 model=switch_on
R sky130_fd_pr__res_generic_m1 model=switch_on
R sky130_fd_pr__res_generic_m2 model=switch_on
R sky130_fd_pr__res_generic_m3 model=switch_on
R sky130_fd_pr__res_generic_m4 model=switch_on
R sky130_fd_pr__res_generic_m5 model=switch_on
R sky130_fd_pr__res_generic_nd R=l/w*120
R sky130_fd_pr__res_generic_pd R=l/w*197
R sky130_fd_pr__res_generic_nd__hv R=l/w*114
R sky130_fd_pr__res_generic_pd__hv R=l/w*191
R sky130_fd_pr__res_generic_po R=l/w*48
R sky130_fd_pr__res_xhigh_po R=l/w*2000
R sky130_fd_pr__res_xhigh_po_0p35 R=l/0.35*2000
R sky130_fd_pr__res_xhigh_po_0p69 R=l/0.69*2000
R sky130_fd_pr__res_xhigh_po_1p41 R=l/1.42*2000
R sky130_fd_pr__res_xhigh_po_2p86 R=l/2.86*2000
R sky130_fd_pr__res_xhigh_po_5p73 R=l/5.72*2000
R sky130_fd_pr__res_high_po R=l/w*300
R sky130_fd_pr__res_high_po_0p35 R=l/0.35*300
R sky130_fd_pr__res_high_po_0p69 R=l/0.69*300
R sky130_fd_pr__res_high_po_1p41 R=l/1.42*300
R sky130_fd_pr__res_high_po_2p86 R=l/2.86*300
R sky130_fd_pr__res_high_po_5p73 R=l/5.72*300
R sky130_fd_pr__res_iso_pw R=l/w*4400

MN sky130_fd_pr__nfet_01v8 Vth=0.2 Vgs=1.8 Vds=1.8
MN sky130_fd_pr__nfet_01v8_lvt Vth=0.1 Vgs=1.8 Vds=1.8
MN sky130_fd_pr__special_nfet_latch Vth=0.2 Vgs=1.8 Vds=1.8
MN sky130_fd_pr__special_nfet_pass Vth=0.2 Vgs=1.8 Vds=1.8
MN sky130_fd_pr__nfet_03v3_nvt Vth=0.2 Vgs=3.3 Vds=3.3
MN sky130_fd_pr__esd_nfet_g5v0d10v5 Vth=0.2
MN sky130_fd_pr__nfet_05v0_nvt Vth=0.2
MN sky130_fd_pr__nfet_g5v0d10v5 Vth=0.2
MN sky130_fd_bs_flash__special_sonosfet_star Vth=0.2

MP sky130_fd_pr__pfet_01v8 Vth=-0.2 Vgs=1.8 Vds=1.8
MP sky130_fd_pr__pfet_01v8_lvt Vth=-0.1 Vgs=1.8 Vds=1.8
MP sky130_fd_pr__pfet_01v8_hvt Vth=-0.3 Vgs=1.8 Vds=1.8
MP sky130_fd_pr__special_pfet_pass Vth=-0.2 Vgs=1.8 Vds=1.8
MP sky130_fd_pr__special_pfet_latch Vth=-0.2 Vgs=1.8 Vds=1.8
MP sky130_fd_pr__pfet_g5v0d10v5 Vth=-0.2

C sky130_fd_pr__cap_mim_m3_1
C sky130_fd_pr__cap_mim_m3_2
C sky130_fd_pr__cap_var
C sky130_fd_pr__cap_var_lvt

Q sky130_fd_pr__pnp_05v5
Q sky130_fd_pr__pnp_05v5_W0p68L0p68
Q sky130_fd_pr__pnp_05v5_W3p40L3p40
Q sky130_fd_pr__npn_11v0
Q sky130_fd_pr__npn_11v0_W1p00L1p00

==> sky130A/fix_spice <==

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#! /bin/bash

sed -<http://i.org|i.org> -e 's/sky130_fd_pr__pnp_05v5_W3p40L3p40/sky130_fd_pr__pnp_05v5 W=3.40 L=3.40/' \
        -e 's/sky130_fd_pr__pnp_05v5_W0p68L0p68/sky130_fd_pr__pnp_05v5 area=3.25/' \
        -e 's/sky130_fd_pr__res_high_po_0p35/sky130_fd_pr__res_high_po W=0.35/' \
        -e 's/sky130_fd_pr__res_high_po_0p69/sky130_fd_pr__res_high_po W=0.69/' \
        -e 's/sky130_fd_pr__res_high_po_1p41/sky130_fd_pr__res_high_po W=1.41/' \
        -e 's/sky130_fd_pr__res_high_po_2p85/sky130_fd_pr__res_high_po W=2.85/' \
        -e 's/sky130_fd_pr__res_high_po_5p73/sky130_fd_pr__res_high_po W=5p73/' \
        -e 's/sky130_fd_pr__res_xhigh_po_0p35/sky130_fd_pr__res_xhigh_po W=0.35/' \
        -e 's/sky130_fd_pr__res_xhigh_po_0p69/sky130_fd_pr__res_xhigh_po W=0.69/' \
        -e 's/sky130_fd_pr__res_xhigh_po_1p41/sky130_fd_pr__res_xhigh_po W=1.41/' \
        -e 's/sky130_fd_pr__res_xhigh_po_2p85/sky130_fd_pr__res_xhigh_po W=2.85/' \
        -e 's/sky130_fd_pr__res_xhigh_po_5p73/sky130_fd_pr__res_xhigh_po W=5.73/' $*

==> sky130A/remove_well.sed <==

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s/[^ ]* \(sky130_fd_pr__.fet\)/\1/
s/[^ ]* \(sky130_fd_pr__special_.fet\)/\1/
s/[^ ]* \(sky130_fd_pr__esd_.fet\)/\1/
s/[^ ]* \(sky130_fd_pr__res_high_po\)/\1/
s/[^ ]* \(sky130_fd_pr__res_xhigh_po\)/\1/
s/[^ ]* \(sky130_fd_pr__res_generic_nd\)/\1/
s/[^ ]* \(sky130_fd_pr__res_generic_pd\)/\1/
s/[^ ]* \(sky130_fd_pr__res_iso_pw\)/\1/
s/[^ ]* \(sky130_fd_pr__cap_var_lvt\)/\1/
s/[^ ]* \(sky130_fd_bs_flash__special_sonosfet_star\)/\1/
s/[^ ]* \(ppolyf_u_1k_6p0\)/\1/
s/[^ ]* \(ppolyf_u\)/\1/
s/[^ ]* \(.fet_06v0\)/\1/
/^D.* sky130_fd_pr__diode_pd2nw_/d
/^D.* sky130_fd_pr__diode_pw2nd_/d
/^D.* diode_pd2nw_06v0/d
/^D.* diode_nd2ps_06v0/d
/^D.* np_6p0/d
/^D.* pn_6p0/d
/^X.* sky130_fd_pr__pnp_05v5/d

And then let me know if there are any more problems in precheck?

vks

11/05/2023, 7:26 AM

I did the steps as mentioned in your last reply. LVS error is still there in

precheck.log

and new OEB error is also added. Attaching logs zip folder for reference. Since LVS of my

user_project_analog_wrapper

is clearing in standalone netgen run with only property errors and LVS is not checked in online precheck submission , Can I go ahead with submitting current design as such? Submission deadline is approaching.

logs.zip

vks

11/05/2023, 7:27 AM

lvs_config.json

vks

11/05/2023, 7:29 AM

cvc.models,fix_spice,remove_well.sed

cvc.models fix_spice remove_well.sed

Mitch Bailey

11/05/2023, 11:58 AM

It’s a json error,

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2023-11-05 06:19:35 - [ERROR] - <class 'json.decoder.JSONDecodeError'>
2023-11-05 06:19:35 - [ERROR] - ("Expecting ',' delimiter: line 11 column 17 (char 318)",)
2023-11-05 06:19:35 - [ERROR] - Error with file /home/vks/ssp_testchip/lvs/user_analog_project_wrapper/lvs_config.json

You probably want to add a

after

tapvpwrvgnd

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"EXTRACT_ABSTRACT": [
                "*__fill_*",
                "*__fakediode_*",
                "*__tapvpwrvgnd_*",
                "io_metal_patch_array_16x16"
        ],

vks

11/05/2023, 3:27 PM

'OEB', 'LVS' Error are still there.

precheck.log

Mitch Bailey

11/05/2023, 3:29 PM

Can you share these files?

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precheck_results/05_NOV_2023___12_30_58/logs/OEB_check.log
precheck_results/05_NOV_2023___12_30_58/logs/LVS_check.log
precheck_results/05_NOV_2023___12_30_58/tmp/lvs.report

vks

11/05/2023, 3:33 PM

Files attached.

LVS_check.log OEB_check.log lvs.report

Mitch Bailey

11/05/2023, 4:05 PM

@vks Looks like the oeb check may be a little old. Those errors should become warnings in the next update (maybe tomorrow). The LVS errors are due to an older version of the tech file and magic. Are you sure you have this line in your

lvs/user_analog_project_wrapper/lvs_config.json

file?

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"LVS_SPICE_FILES_TO_FIX": [
        "$UPRJ_ROOT/xschem/user_analog_project_wrapper.spice"
        ],

Mitch Bailey

11/05/2023, 4:21 PM

@vks also can you share

precheck_results/<tag>/tmp/cvc.errors.gz

? Analog designs generally have false errors, but I’d like to check to be sure.

vks

11/05/2023, 4:43 PM

Yes, the required line is added in

lvs_config.json

. File is also attached. `cvc.error`also shared.

cvc.error lvs_config.json

Mitch Bailey

11/05/2023, 4:54 PM

Can you check one type of CVC error for me? The following inverters are flagged as having a tristate input. Is that intended?

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* Tri-state input
/Xring_osc_0(ring_osc)/Xdivx32_0(divx32)/Xfreq_div_1(freq_div)/Xinverter_fd_3(inverter_fd)
/Xring_osc_0(ring_osc)/Xdivx32_0(divx32)/Xfreq_div_0(freq_div)/Xinverter_fd_2(inverter_fd)
/Xring_osc_0(ring_osc)/Xdivx32_0(divx32)/Xfreq_div_0(freq_div)/Xinverter_fd_1(inverter_fd)

Mitch Bailey

11/05/2023, 5:01 PM

Can you share your latest

LVS_check.log

along with

precheck_results/<tag>/tmp/lvs.script

? Looks like there are some intentionally shorted ports in the

ring_osc

layout. Can you put that cell in the

LVS_FLATTEN

lvs_config variable?

vks

11/05/2023, 5:06 PM

ring_osc

is taken as macro in my design. I have used it in my design and only made layout connections to its pins. I have put it in

LVS_FLATTTEN

and started precheck run. Will update about its output.

LVS_check.log lvs.script

Mitch Bailey

11/05/2023, 5:17 PM

Can you show me the result of this? It should be changing the schematic model names to match the layout.

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diff xschem/user_analog_project_wrapper.spice precheck_results/<tag>/spice_files/user_analog_project_wrapper.spice

vks

11/06/2023, 12:07 AM

Cannot find

spice_files

folder in

precheck_results/<tag>/

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precheck_results/<tag>/spice_files/user_analog_project_wrapper.spice

Mitch Bailey

11/06/2023, 12:11 AM

Sorry,

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diff xschem/user_analog_project_wrapper.spice precheck_results/<tag>/tmp/spice_files/user_analog_project_wrapper.spice

vks

11/06/2023, 6:16 AM

There is no folder called

spice_files

inside

tmp

folder.

spice_files

is a text file containing path to

precheck_results/05_NOV_2023___12_30_58/tmp/spice_fix/user_analog_project_wrapper.spice

. I ran following command:

diff xschem/user_analog_project_wrapper.spice precheck_results/05_NOV_2023___12_30_58/tmp/spice_fix/user_analog_project_wrapper.spice

and there is no output for this command.

Mitch Bailey

11/06/2023, 10:51 AM

@vks sorry for the confusion. Can you do a

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ls -l $HOME/mpw_precheck/checks/be_checks/tech/sky130A/fix_spice

and make sure that it’s executable?

vks

11/06/2023, 10:53 AM

How to check whether it is executable? I am getting following output:

vks

11/06/2023, 10:53 AM

image.png

Mitch Bailey

11/06/2023, 11:06 AM

Looks executable.

Mitch Bailey

11/06/2023, 11:07 AM

Let me think…

Mitch Bailey

11/06/2023, 2:30 PM

Are you using the latest version of precheck?

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export MPW_TAG=mpw-9f
make precheck
make run-precheck

vks

11/06/2023, 3:20 PM

Getting following output to

make precheck

. Please suggest.

Mitch Bailey

11/06/2023, 4:20 PM

Can you try

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mv $HOME/mpw_precheck $HOME/mpw_precheck.bak

and try again?

Mitch Bailey

11/07/2023, 3:54 AM

@vks I apologize for the confusion about updating the

caravel_user_project

tag. The updated repo has

Makefile

changes. I think the recommended way is to clone a new repo and start over but maybe this way will work, too. 1. Check for and delete any relevant variables.

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env | grep TAG
env | grep COMMIT
env | grep ROOT

I think you should delete any

TAG

and

COMMIT

variables. (

unset <variable>

). Check that the

ROOT

variables are what you expect.

CARAVEL_ROOT,

PRECHECK_ROOT

PDK_ROOT

MCW_ROOT

directories will be deleted and recloned with the new tag. If you have made changes, they will be lost. 2. From your project directory, clone the newly tagged

caravel_user_project

to a new directory and copy the

Makefile

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git clone -b <new_tag> <https://github.com/efabless/caravel_user_project> --depth=1 $HOME/cup-<new_tag>
cp $HOME/cup-<new_tap>/Makefile .

You could use diff to see if any other files have changed and take appropriate action. (you can ignore the

.git

changes)

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diff -r . $HOME/cup-<new_tag> | less

Once you’ve checked the files, you can probably delete the newly cloned directory (

rm -rf $HOME/cup-<new_tag>

) 3.

make setup

vks

11/07/2023, 10:18 AM

@Mitch Bailey Sorry but I am little confused. We started with a problem that LVS of standalone

user_analog_project_wrapper.gds

was clearing but was failing in local precheck. Was it due to some issue with precheck files, if yes what should I do now ? There were few changes made in my setup and

lvs_config.json

file . Do they need to be reverted back?

vks

11/07/2023, 10:19 AM

There is message about release of new precheck. Will that help my problem ?

Mitch Bailey

11/07/2023, 10:23 AM

Right, we made some changes to the precheck files. You can probably put the spice file back under

LVS_SPICE_FILES

. I don’t think

LVS_SPICE_FILES_TO_FIX

is needed. The other changes may still be needed to pass LVS locally and for platform OEB check if that’s failing.

vks

11/07/2023, 11:32 AM

By other changes do you mean these one ? https://open-source-silicon.slack.com/archives/C01E06TUSC9/p1699329278938039?thread_ts=1699085363.405979&cid=C01E06TUSC9 Will these changes update my local precheck files? Can it disturb or overwrite my existing design files. I am new to git and github. How can I use git to keep backup of my existing design database in order to retrieve back to it in case of any issue.

Mitch Bailey

11/07/2023, 12:00 PM

This one https://open-source-silicon.slack.com/archives/C01E06TUSC9/p1699117502079049?thread_ts=1699085363.405979&cid=C01E06TUSC9

vks

11/07/2023, 12:06 PM

Ok, please confirm if following are the steps to be followed: 1. Put spice file back under

LVS_SPICE_FILES

lvs_config.json

file. 2. Put back default files in

$PRECHECK_ROOT

folder 3. run

make run-precheck

vks

11/08/2023, 4:13 PM

@Mitch Bailey I have updated local precheck and ran on my design. Getting

OEB, LVS

errors from this precheck run. Any suggestions on these errors?

precheck.log lvs_config.json

Mitch Bailey

11/10/2023, 12:34 AM

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2023-11-08 15:10:48 - [ERROR] - <class 'json.decoder.JSONDecodeError'>
2023-11-08 15:10:48 - [ERROR] - ('Expecting value: line 12 column 9 (char 357)',)
2023-11-08 15:10:48 - [ERROR] - Error with file /home/vks/ssp_testchip/lvs/user_analog_project_wrapper/lvs_config.json

Try removing the

after

"io_metal_patch_array_16x16"

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"EXTRACT_ABSTRACT": [
                "*__fill_*",
                "*__fakediode_*",
                "*__tapvpwrvgnd_*",
                "io_metal_patch_array_16x16",
        ],

This

io_metal_path_array_16x16

is an inert circuit, right? It’s not connected to anything, is it?

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