I am having trouble with the LVS check with SRAM, there are a lot of mismatches inside the SRAM. For example things like:

Contents of circuit 1:  Circuit: 'ypass_gate_a_512x8m81'
Circuit ypass_gate_a_512x8m81 contains 9 device instances.
  Class: pmos_5p0431059130201_512x8m81 instances:   2
  Class: nmos_1p2$$47119404_512x8m81 instances:   2
  Class: nmos_5p0431059130202_512x8m81 instances:   1
  Class: pfet_03v3             instances:   3
  Class: pmos_1p2$$46889004_512x8m81 instances:   1
Circuit contains 10 nets.
Contents of circuit 2:  Circuit: 'ypass_gate_a_512x8m81'
Circuit ypass_gate_a_512x8m81 contains 9 device instances.
  Class: pmos_5p0431059130201_512x8m81 instances:   2
  Class: nmos_1p2$$47119404_512x8m81 instances:   2
  Class: nmos_5p0431059130202_512x8m81 instances:   1
  Class: pfet_03v3             instances:   3
  Class: pmos_1p2$$46889004_512x8m81 instances:   1
Circuit contains 13 nets.

Circuit 1 contains 9 devices, Circuit 2 contains 9 devices.
Circuit 1 contains 10 nets,    Circuit 2 contains 13 nets. *** MISMATCH ***

Not sure if I should be running LVS on the SRAM or not, I tried adding the SRAM cell to the LVS_IGNORE list, then the LVS would report “Circuits match uniquely” with a few warnings saying the SRAM has been ignored, but the pre-check still flags LVS as failed. Any suggestions?

@Wenting Zhang Try using this config file. Copy it to

lvs/user_project_wrapper/lvs_config.sram512x8m8wm1.json

And then modify

lvs/user_project_wrapper/lvs_config.json

as follows

{
  "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
  "INCLUDE_CONFIGS": [
    "$LVS_ROOT/tech/$PDK/lvs_config.base.json",
    "$UPRJ_ROOT/lvs/$TOP_SOURCE/lvs_config.sram512x8m8wm1.json"
  ],
  "TOP_SOURCE": "user_project_wrapper",
  "TOP_LAYOUT": "$TOP_SOURCE",
  "EXTRACT_FLATGLOB": [
    ""
  ],
  "EXTRACT_ABSTRACT": [
    ""
  ],
  "LVS_FLATTEN": [
    ""
  ],
  "LVS_NOFLATTEN": [
    ""
  ],
  "LVS_IGNORE": [
    ""
  ],
  "LVS_SPICE_FILES": [
    ""
  ],
  "LVS_VERILOG_FILES": [
    "$UPRJ_ROOT/verilog/gl/user_proj_example.v",
    "$UPRJ_ROOT/verilog/gl/user_project_wrapper.v"
  ],
  "LAYOUT_FILE": "$UPRJ_ROOT/gds/user_project_wrapper.gds"
}

Thanks, I tried right away, but almost one day later the magic is still running extraction…

What version of magic? There was a problem with a slightly older version getting stuck in a loop. It has been fixed.

It reports Magic 8.3 revision 420 - Compiled on Tue Oct 31 200654 UTC 2023. I am using the precheck docker image installed by the caravel Makefile

Probably should be at least 442. I’ll let Marwan know. Thanks for reporting.

Is the new precheck release supposed to fix this issue? I just pulled the lastest precheck docker image, it now reports Magic 8.3 revision 420 - Compiled on Sat Nov 4 210317 UTC 2023. Looks I am definitely getting the new image (with newer build date) but still old version of Magic?

I’d logged an issue, but doesn’t look like it’s been fixed yet. 🙁 Sent a message, too.

I would also like to run LVS with the SRAM, it seems like there is already a PR open: https://github.com/efabless/mpw_precheck/pull/255 😃️ I have a question regarding your `lvs_config.json`: In the section

LVS_VERILOG_FILES

, do I need to add the gl files for my other macros as well?

Yes, in order to run LVS, you’ll need to add the gl verilog or spice files for every macro to the

lvs_config.json

file(s).

I am also facing issue with LVS around SRAM, Look like PR related to Magic version is not checked in ? I see "LVS_IGNORE" has no impact on LVS check, what is alternative suggestion here ?

@Dinesh A sorry, I can’t think of any easy fixes. If you really wanted to test your design locally, you could fork

mpw_precheck

to your github, merge the pull requests, and then clone the repo manually to your

PRECHECK_ROOT

.

Yes, that's what I did, I built the docker image locally. As for when the docker image will be updated, I asked in the shuttle-precheck channel, but it seems that everyone is currently busy preparing the tapeout for sky130: https://open-source-silicon.slack.com/archives/C01E06TUSC9/p1699507592539909