open-source-silicon.dev

TOP_mixed.v

user_project_wrapper.v

TOP_digital.v

These are the verilog files we have given it (the Analog module is in spice, and Netgen is happy about that one):

lvs.report

The mismatches on the right column look like they are coming from `user_project_wrapper.v`, where TOP_mixed is instantiated. Its unhappy about all these pins (in reverse order).

image.png

The left mismatches look like they are coming from `user_project_wrapper.gds.spice`, again in the TOP_mixed module and in reversed order.

Not sure if this is actually the problem, or just a netgen artifact from a different problem. But looking at the LVS report I actually cannot see any errors between the two circuits, and the soft.log shows 0 problems. Also circuits matched uniquely before TOP_digital.v was added. Very confused

lvs_config.json

TOP_analog.spice

<@U017X0NM2E7> and here's the analog spice just incase :slightly_smiling_face:

<@U03SX0UNJRZ> Your verilog files need to be in order from lowest to highest. Can you try with `TOP_digital` before `TOP_mixed`?

<@U017X0NM2E7> that's fixed it!! Thank you so much. I was going a bit crazy staring at those busses

Yes. I’ve been there… several times.:nauseated_face:

<@U017X0NM2E7> Just wanted to double check something with you as I've recieved conflicting advice. Our next step is to populate `TOP_analog` with all of our analog devices and subcells (which have passed LVS separately). Then we are sharing the area with 2 other designers. Someone said we only need to include a description of our the top level Macros for LVS - in our case, this would be `TOP_mixed` - but I was of the understanding we need to include a description (verilog or spice) for _every module_ in our design - (ie - TOP_digital, TOP_analog, + every device within TOP_analog, all the way down the hierarchy). Please could you advise which is correct?

I know that the LVS flow will flag a warning if there are unflattened cells mentioned somewhere.. I'm guessing their suggestion is to not reference the subcells and only include a description of the top level Macro and its connections to user_project_wrapper?

For LVS inside openlane, you only need the top level macros - there is no way currently to specify lower level subcircuits. For LVS in the local precheck, you’ll need all the modules. The precheck LVS does not run on the platform and thus is not strictly necessary for chipIgnite designs.