@Mitch Bailey @Tim Edwards Hi I am getting few checks failed while submitting the gds to MPW precheck Out of 12 check 2 failed 1. NETLIST CONSISTENCY CHECK FAILED 2. KLAYOUT FEOL CHECK FAILED : can you please help what is the fix required to do log files for the reference

I can't get much information from the log files other than klayout is reporting errors on the HVI layer, which is something that might not show up in magic's DRC but might show up as an error during GDS write or during extraction. Since HVI is an auto-generated layer in magic, it's harder to debug issues. The set of log files that you posted does not contain any information regarding the netlist consistency check. Do you have a valid netlist in the user project?

Hi Tim, Any way to fix the DRC issue, I will check the netlist from my side once

There are multiple ways to fix the DRC issues once you know what they are. They have to be identified and understood.

What is the meaning of a valid netlist?my design is analog and I only update the gds for check

A valid netlist would be for example an xschem schematic-captured SPICE netlist.

@samarth jain Can you put your

user_analog_project_wrapper.spice

file in the

netgen

directory? I think precheck is checking for a file there.

My design is done in cadence and not using open source software @Mitch Bailey

Do you have a spice netlist that you use for LVS? I think that might work.

We have mix signal design,has analog and digital.it’s hard to make single netlist.but from our end we have checked netlist @Mitch Bailey

Do you have Calibre? If so, v2lvs will change your verilog to a spice netlist that you can put in netgen. Actually, you can probably just copy

xschem/user_analog_project_wrapper.spice

to

netgen

.

Xschem ?I am using cadence @Mitch Bailey

If you cloned the

caravel_analog_user_project

there should be an old

xschem/user_analog_project_wrapper.spice

file there. The precheck is just looking for a file. It doesn’t have to be the right file.

I see

@samarth jain sorry, I thought you were using analog. The digital consistency check should give you more information. Maybe like the hierarchy doesn’t match or power pins are not defined. Do you see any detailed messages in the log?

Not much details r given in log @Mitch Bailey ,I have also attached my log files

From

precheck.log

2023-11-02 13:01:00 - [WARNING] - LAYOUT CHECK FAILED: The GDS layout for user_project_wrapper doesn't match the provided structural netlist. Mismatching modules are: ['M3M4_CDNS_698929035730' 'RRAM_WRAPPER']

Looks like there’s some blocks in the layout that aren’t in the verilog. Does this design have reram? The precheck logs look like it’s sky130A which doesn’t include reram? Do you want sky130B?

Yes, it has reram

Be sure to set your PDK to sky130B and recreate all your gds. Check your final gds to be sure that the reram layer is there.

using s130 for rram @Mitch Bailey which I also used for my previous tapeout

Do you have a working chip back? I noticed on there were missing reram layers on some designs. What process did you choose on the platform?

Which platform?there is no option to pick chip platform on efabless.I just use pdk provided by skywater for cadence with rram .No my chip is under fabrication and I assumed efabless would check as I had informed about rram

When a ChipIgnite project has the ReRAM layer, SkyWater splits the lot and sends some of the wafers for ReRAM processing. The projects with ReRAM will be picked from those wafers, and the ones without ReRAM will be picked from the other wafers.