Hello, I don't understand OPENROAD Atenna Rule Check clearly. In my design I don't use atena. so I removed the atena related parameters in config.json. I got a break at this step with the error: [ERROR]: There are violations in the design at the typical corner. Please refer to '../home/nam/edabk_new_project/efabless/caravel_user_project/openlane/user_project_wrapper_ver_1/runs/23_11_02_04_42/reports/signoff/21-rcx_sta.min.rpt'. Please help me

The antennas form during the making of the chip. First the transistors are made, then the metal 1 connections, then metal 2 and so on. To have so many layers the wafer has to be polished between each step or the higher layers will be too bumpy. Unfortunately, if a transistor is connected to a distant one through several metal layers but these layers haven't been made yet then the dangling wires (imagine that two metal 3 segments will be connected by a future metal 4 segment) are antennas that will attract electrical charge during the polish process. This charge can damage the transistor connected to this temporary antenna so the solution is to add a diode to ground which will divert this charge and protect the transistor.

Can you help me clarify specifically? I haven't figured out how to add a diode to ground to redirect this charge and protect the transistor. My design doesn't use atena, do I still have to use it? I don't have much experience in this

steven darker, the “antenna” rules are to prevent device degradation that can occur during the fabrication process. It has nothing to do with antennas that are used for RF chips. As @Jecel Assumpção Jr explained, each etching step causes a charge build up on poly and metal that causes cumulative damage to the transistor gates. The longer the wires connected to the gate, the more the damage. The antenna check is done at each metal layer cumulatively. For example, metal1 includes poly, metal2 include poly and metal1, etc. If the total metal-poly ratio is greater than the rule limit, an error is flagged. The error can be mitigated by connecting the wire to a diode or source/drain. Any nets connected to diffusion are removed from the check.

Steven Darker, as David and I said the antennas are not part of your design on purpose but form halfway through the fabrication process and then go away as the final metal layers are added. If you are using OpenLane for a standard cell design then the normal configuration will add any needed protection diodes for you. If you are instead doing your down analog design in, for example, Magic then you will have to deal with this yourself.

yes I am clear about the antenna. But is there any way for me to fix the problem in the OPENROAD ANTENA RULE CHECK step? Can you suggest me some cases to fix it?

@steven darker the error is not occurring in step 31. The error is occurring in step 21. However, the flow is not failing at step 21, but proceeding to generate the final data.

Of course. I see that the signoff process is the cause of this bad thing. Please suggest me how to fix it

@steven darker one of the problems is that the default config does not do any resizing at the top level - it just connects things. So if you have one top level signal connecting to many macros, you’re probably going to get fanout errors. I haven’t actually had any actual experience with this type of design, but I imagine you can either change the configuration to synthesize the top design or add another level to your design that has all the macro with timing constraints met. Changing the top level configuration requires a detailed knowledge of the configuration variables and their interactions. However, adding another level may not be possible depending on how deep your current level is. Are you able to share your config files?

Of course. This is my config file

So you’re just placing one macro. Are you connecting several pins of the macro to a single net at the top level? I imagine that could cause fanout errors. Can you see the name of the net where the errors are occuring?