Hi, although I labeled the pins, after the extraction for LVS I get the pin mismatch error.

@Amirhossein zanjani Just a guess here. Normally, the layout is on the left and the source is on the right. If you used xschem to create the schematic netlist, be sure to set

Simulation

->

LVS netlist: top level is a .subckt

before netlisting.