@Mitch Bailey Is it ok to submit design for Chipignite shuttle without performing LVS check during precheck ? If yes, how can LVS check be ignored in precheck ?

Is there a specific reason you don't want to perform LVS?

I have put some test structure devices which don't need LVS at top level. Hence won't to avoid running LVS at

user_project_analog_wrapper

level.

Well LVS doesn't run on the platform anyways, it only runs locally. To avoid running it locally you can

export DISABLE_LVS=1

. But I have to advise against disabling full LVS on the top level.

@vks You can edit the

lvs/user_analog_project_wrapper/lvs_config.json

file to ignore cells with test structures.

@Mitch Bailey I have 4 designs in total. Want to ignore only one by name "test_structure". What should be syntax for it in

lvs_config.json

file ?

{
  "STD_CELL_LIBRARY": "sky130_fd_sc_hd",
  "INCLUDE_CONFIGS": [
    "$LVS_ROOT/tech/$PDK/lvs_config.base.json"
  ],
  "TOP_SOURCE": "user_analog_project_wrapper",
  "TOP_LAYOUT": "$TOP_SOURCE",
  "EXTRACT_FLATGLOB": [
    ""
  ],
  "EXTRACT_ABSTRACT": [
    ""
  ],
  "LVS_FLATTEN": [
    ""
  ],
  "LVS_NOFLATTEN": [
    ""
  ],
  "LVS_IGNORE": [
    "test_structure"
  ],
  "LVS_SPICE_FILES": [
    "$UPRJ_ROOT/xschem/user_analog_project_wrapper.spice"
  ],
  "LVS_VERILOG_FILES": [
    ""
  ],
  "LAYOUT_FILE": "$UPRJ_ROOT/gds/user_analog_project_wrapper.gds"
}

Can you try this?

Thanks @Mitch Bailey, I will try this. If a block has different names in schematic and layout? For example, it is called "test_structure" in layout but "test_str" in schematic; how to ignore it using

LVS_IGNORE

?

You could use

"LVS_IGNORE": [
                "test_str*"
        ],

or

"LVS_IGNORE": [
                "test_str",
                "test_structure"
        ],

Thanks very much @Mitch Bailey. This will take care of LVS during pre-check. How can I ignore "test_structure" block while running LVS on

user_analog_project_wrapper

layout using below netgen command. What will be the syntax to ignore "test_structure" block from LVS ?

netgen -batch lvs "../mag/user_analog_project_wrapper.spice user_analog_project_wrapper"  "../xschem/user_analog_project_wrapper.spice user_analog_project_wrapper" /usr/local/share/pdk/sky130A/libs.tech/netgen/setup.tcl comp.out

You need to modify

/usr/local/share/pdk/sky130A/libs.tech/netgen/setup.tcl

(copy it locally first). Look at the end of the

precheck_results/<tag>/tmp/sky130A_setup.tcl

file.

@Mitch Bailey I looked at

precheck_results/<tag>/tmp/sky130A_setup.tcl

file but could not understand which section to modify in locally copied

setup.tcl

file to ignore particular block during LVS. Please suggest.

Looks like the script can’t find the cell in the layout. Is the ignore cell in

precheck_results/<tag>/tmp/layout.cells

?

Ignored cell name is "io_metal_patch_array_16x16". it is not there in

layout.cells

file.

Gds cells with less than 10 shapes are automatically flattened. However, the

layout.cells

list is taken from the gds. Is it in the schematic? Can you try removing the

*

at the end? Wild cards cause a search, but fixed strings should be processed as is.

I did as suggested used update

lvs_config.json

file but no change in list of cells inside

layout.cells

file.

Right. Layout cells won’t change. Does

precheck_results/<tag>/tmp/sky130A_setup.tcl

show anything at the end of the file?

Sorry but I cannot understand what to look at end of the file. I have attached the file for your reference.

It should be added after line #538

#Added programatically.

but I don’t see anything either. Is there anything in

precheck_results/<tag>/tmp/ignore.glob

or

precheck_results/<tag>/tmp/ignore

?

Both the files

ignore

and

ignore.glob

are empty

1. Can you share

lvs/user_analog_project_wrapper/lvs_config.json

2. Can you share the latest

precheck_results/<tag>/logs/*check.log