I think that's not the problem. Because my RAM si...
# openlanes
steven darker
10/30/2023, 7:29 AMI think that's not the problem. Because my RAM size is 32GB and it only used 23GB
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Vijayan Krishnan
10/30/2023, 7:36 AMare you trying for mpw shuttle mean, file an issue with test case
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steven darker
10/30/2023, 7:45 AMI created an IP module in the caravel user project. When synthesizing with openlane, it appears idle as I described
steven darker
10/30/2023, 7:46 AMI tried simulating that IP with questa sim and it ran correctly as required
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Vijayan Krishnan
10/30/2023, 7:46 AMhow long it is running at step 1?
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steven darker
10/30/2023, 7:49 AMFrom the moment I told you until now. Over 50 minutes... and it stays there
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Mitch Bailey
10/30/2023, 12:44 PMAre you using openRAM macros? If you are, you’ll probably want to define those as black boxes.
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steven darker
10/31/2023, 9:51 AMI want to synthesize a very large AI design, SRAM size is 2048x32. Therefore, running 1 core to synthesize the design will take a long time. So is there any way to increase synthesis performance?. I have 48 cores and I really want to use them all for this process
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