Hello, I'm encountering issues with the OpenLane flow. Upon executing the command "flow.tcl -design ...
p
Hello, I'm encountering issues with the OpenLane flow. Upon executing the command "flow.tcl -design ../top -tag test1", I encounter a problem that I've been unable to resolve. This is puzzling, as a previous module ran successfully. However, after incorporating this module into the top design without significant modifications, the aforementioned error arises.
m
@Patricio Carrasco Do you have enough memory?
p
Hello @Mitch Bailey , I am using the docker "IIC-OSIC-TOOLS" and I think I have enough memory, I have 16gb
m
Are there any further details in the detailed log files? Look in
runs/<tag>/logs
Could it be related to this issue? It’s currently closed, but someone posted 2 weeks ago. If you think it’s still a problem, you might reopen it.
p
I'm sorry @Mitch Bailey, I still can't fix it. I have these two files, top.v and out.v, which are almost identical. The key difference is that the main module from out.v is re-instantiated in top.v, and this cause the error. Strangely, when I run just out.v, everything works seamlessly. However, when it's integrated into top.v, I face issues.
m
Sorry @Patricio Carrasco, I don’t have much verilog experience.
p
@Mitch Bailey Thank you likewise for your time.