Hi I am doing the top level integration of multiple blocks u open-source-silicon.dev #shuttle

Hi! I am doing the top-level integration of multi...

Rodrigo Wuerdig

10/29/2023, 10:06 PM

Hi! I am doing the top-level integration of multiple blocks using caravel and I am struggling with the LVS Errors at step 29 (attached). It looks like a problem with the:

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"FP_PDN_MACRO_HOOKS": [
        "egd_top_wrapper vccd1 vssd1 vccd1 vssd1",
        "R4_butter       vccd1 vssd1 vccd1 vssd1",
        "wb_buttons_leds vccd1 vssd1 vccd1 vssd1"],

That is maybe considering vccd1 and vssd1 as 6 different nets. Does anyone know how to solve that? All the files can be seem at https://github.com/unic-cass/IC1-CASS

config.json 29-lvs.lef.log

Mitch Bailey

10/30/2023, 12:15 AM

You’re missing a comma before the

. Try

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"FP_PDN_MACRO_HOOKS": [
        "egd_top_wrapper vccd1 vssd1 vccd1 vssd1,",
        "R4_butter       vccd1 vssd1 vccd1 vssd1,",
        "wb_buttons_leds vccd1 vssd1 vccd1 vssd1"],

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Rodrigo Wuerdig

10/30/2023, 12:31 AM

Thanks! I will try that!

Rodrigo Wuerdig

10/30/2023, 12:44 AM

No luck 😞 But it changed the amount of nets that were not matching. Before it was: 219 vs 215 nets and now is: 217 vs 215 nets I will try to 'make setup' and try again

29-user_project_wrapper.lef.lvs.log 29-user_project_wrapper.lef.lvs.json 29-lvs.lef.log

Mitch Bailey

10/30/2023, 2:25 AM

Can you share

runs/23_10_29_21_33/logs/signoff/29-user_project_wrapper.lef.lvs.log

Rodrigo Wuerdig

10/30/2023, 12:10 PM

Yes. Here it is

29-user_project_wrapper.lef.lvs.log

Mitch Bailey

10/30/2023, 2:11 PM

First, the pins don’t match on

wb_buttons_leds

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o_wb_stall                                 |(no matching pin)

o_wb_stall

is in the layout but not the source. and your

wb_buttons_leds

macro is not powered

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Net: vccd1                                 |(no matching net)                          
  R4_butter/vccd1 = 1                      |                                           
  egd_top_wrapper/vccd1 = 1                |                                           
                                           |                                           
Net: vssd1                                 |(no matching net)                          
  R4_butter/vssd1 = 1                      |                                           
  egd_top_wrapper/vssd1 = 1                |                                           
                                           |                                           
Net: wb_buttons_leds/vccd1                 |(no matching net)                          
  wb_buttons_leds/vccd1 = 1                |                                           
---------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------
(no matching net)                          |Net: vssd1                                 
                                           |  R4_butter/vssd1 = 1                      
                                           |  egd_top_wrapper/vssd1 = 1                
                                           |  wb_buttons_leds/vssd1 = 1                
                                           |                                           
(no matching net)                          |Net: vccd1                                 
                                           |  R4_butter/vccd1 = 1                      
                                           |  egd_top_wrapper/vccd1 = 1                
                                           |  wb_buttons_leds/vccd1 = 1

Take a look at the layout to see if you can tell why. It may be that the macro is too short and doesn’t cross the necessary power rails. If so, you could reposition it so it does cross.

Rodrigo Wuerdig

10/30/2023, 2:19 PM

Thanks a lot! I will have a look on that.

Rodrigo Wuerdig

10/30/2023, 2:52 PM

it looks like the block has a delimitation and the pdn doesnt go over it could it be a misalignment? At the macro.cfg should I use a number that is multiple of something?

👍 1

Rodrigo Wuerdig

10/30/2023, 3:19 PM

I think I found the problem. The group synthesized the block without the

desing_is_core

flag. So it is probably conflicting with the PDN at MET4 and MET5. They are redoing the synthesis. Thanks a lot for your help!

Rodrigo Wuerdig

11/01/2023, 1:33 AM

The root of my problems was mixing mpw-9e with mpw-9d parts...

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Rodrigo Wuerdig

11/01/2023, 12:41 PM

Unfortunately I stumbled upon a hold timing issue at the wishbone interface. My guess is that the cause is due to the clock uncertainty at

wb_clk_i

+ zero delay at

wb_addr_i

and

wbs_dat_i

. If someone knows how to solve that... I've tried to put the block that is using the wb very close to the pins but I got no luck with that...

20-rcx_sta.min.rpt

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