Hi, Our design passes the olane flow with max sle...
# chipignite
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Hi, Our design passes the olane flow with max slew, cap and fanout warnings. I did not change any default config parameter related to slew, cap or fanout. I checked rcx_sta report file: max slew Limit is 1.50 and slew values are 2.19 for all violated pins max fanout Limit is 10, one pin has 36, one pin has 24 and other violations fanout is 16. 36 fanout pin is reset signal, 24 fanout pin is a common IO isolation pin. Other 16 fanout violation pins are internal. max cap Limit is 0.13 and violated pins has 0.19 for all. The design get max slew violation count 350 max fanout violation count 74 max cap violation count 175 We are planning Nov.6 chipignite tapeout. Is it OK to go with these warnings, or should we get rid of them? If we should, how? Regards, NOTE: I asked this to openlane hashtag, but couldn't get rid of these warnings. So, I am just asking going chipignite tapeout with these warnings a problem ? https://open-source-silicon.slack.com/archives/C016H8WJMBR/p1698388711652429
@jeffdi @Tim Edwards ?
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I think these look okay, based on the report. The max fanout should not be an issue as long as the STA analysis says that this is not causing a huge slew or cap violation. The slew violation of 2.19 is high but not terrible, and the max cap limit is only being violated by a small amount. It is really a question that needs to be answered by the openlane development team, as I am not the expert voice here.