Hello. I encountered an error while performing LVS for my circuit. After checking the error and finding that pin matching was incorrect, I examined the

comp.out

file and noticed that

cdac_vn

and

cdac_vp

were mismatched. I don't understand the layout itself is incorrect. However, when I made changes two port each, the error count increased but didn't resolve the problem. What steps should I do to solve the error? I attached images and files for reference. Any assistance would be greatly appreciated.

@권용진학부생 It looks like there might be 2 problems. 1. There’s a 2 input nand gate with

X_drive

and

Y_drive

as inputs. In the schematic,

X_drive

is input to the nmos with

VSS

source while in the layout, the net corresponding to

Y_drive

is input to the nmos with

VSS

source. In netgen, logic gate input permutation is not allowed. 2. In the schematic,

X_inv

drives

RS_n

and

Y_inv

drives

RS_p

while in the layout

X_inv

drives

RS_p

and

Y_inv

drives

RS_n

.

@Mitch Bailey Thank you. I check my mistake and modify my layout. However, I had one more error. I draw

ready

port in layout like attatched image. but, comp.out said

(no matching pin)

. Addtionally, It looks like 2 ready ports. I didn't change the schemtic spice file named

hgu_comp.spice

. What can I do for solving this error? I attatched files and images.

@권용진학부생 the

ready

port shows up twice in the report file when not matched. It’s a little confusing, but something we live with at the moment. The problem is that the

ready

port in the layout is not being extracted. I’m not sure why. Is there a message in the extraction log that it shorted to another net?

@Mitch Bailey There is no extraction log about anything. It just extract like attached image.

Check the label coordinates and the label layer.

@Mitch Bailey I follow your advice. so I found it error. I think

Offset from reference

and

Attaach to layor

are problem. Thank you so much for your help.

@Tim Edwards,do you have a link to a very simple github repo containing a trivial circuit (may be an inverter or a simple differential amplifier or such) and the corresponding layout that should pass LVS with Magic/Netgen (sky130) ? I get so numerous emails from hopeless people, and it should help a lot!.

@Stefan Schippers: How about this one? https://github.com/RTimothyEdwards/tutorial_layout. . . It's your circuit. : ) From the layout tutorial I did from the op-amp you made in your schematic tutorial. It's not trivial but it's relatively simple, and it's available. I confirmed that I can still clone it and do

./run_lvs.sh

and it still extracts correctly and passes LVS.

@Tim Edwards Thank you, will forward the link! I almost forgot this work (and remember now I did also see the presentation for the layout followup). So my apologies!.