Hi, I was trying to do a Muller C (https://en.wikipedia.org/wiki/C-element) but fail in the synthesis step because this logic needs and have a loop, anyone knows how can I declare combinational logic with loops? Console Error:

[ERROR]: Yosys checks have failed: Encountered check error:
Warning: found logic loop in module MULLERC_6:
    cell $and$/openlane/designs/MULLER_C_6/src/MULLERC_6.v:39$6 ($and)
    cell $or$/openlane/designs/MULLER_C_6/src/MULLERC_6.v:39$12 ($or)
    wire $and$/openlane/designs/MULLER_C_6/src/MULLERC_6.v:39$6_Y
    wire \ACK

child process exited abnormally
[ERROR]: See the full report here: designs/MULLER_C_6/runs/RUN_2023.10.23_21.22.13/reports/synthesis/1-synthesis_pre_synth.chk.rpt
[ERROR]: Step 1 (synthesis) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
    while executing
"throw_error"
    (procedure "check_synth_misc" line 13)
    invoked from within
"check_synth_misc $report"
    (procedure "run_synthesis_checkers" line 5)
    invoked from within
"run_synthesis_checkers $log $pre_synth_report"
    (procedure "run_synthesis" line 19)
    invoked from within
"run_synthesis"} -errorline 1

1-synthesis_pre_synth.chk.rpt file:

21. Executing CHECK pass (checking for obvious problems).
Checking module MULLERC_6...
Warning: found logic loop in module MULLERC_6:
    cell $and$/openlane/designs/MULLER_C_6/src/MULLERC_6.v:39$6 ($and)
    cell $or$/openlane/designs/MULLER_C_6/src/MULLERC_6.v:39$12 ($or)
    wire $and$/openlane/designs/MULLER_C_6/src/MULLERC_6.v:39$6_Y
    wire \ACK
Found and reported 1 problems.

My MPW1 design was asynchronous and other than having to declare a random clock to make STA happy I don't remember having to do anything special to get by Yosys