Searching through threads here, I've seen that when

VSUBS

shows up in the netlist extracted (for

lvs

) from Magic, that means that we didn't connect up the substrate... Well, the thing in our case is the following: 1. we have 5 subcells (one of them a simple opamp), each designed on its own, each carefully and thoroughly checked against DRC and LVS 2. we have put those 5 subcells in a top cell magic file and routed them together. 3. we connected all the grounds together in Magic layout just the same as in Xschem top cell schematic 4. during extraction of independent subcells we never saw any report of

VSUBS

5. when doing

extract all
ext2spice lvs
ext2spice

on the top cell, we get a spice netlist that puts

VSUBS

instead of the gnd node in the opamp (called

ground

, we didn't use global nodes)... When we do LVS, for 4 subcells we get:

Flattening unmatched subcell sky130_fd_pr__res_xhigh_po_0p69_XZX24Q in circuit dac_cell2 (1)(4 instances)
Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_FGUWVM#1 in circuit dac_cell2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_FGK6VM in circuit dac_cell2 (1)(3 instances)

Class dac_cell2 (0):  Merged 2 parallel devices.
Class dac_cell2 (0):  Merged 1 series devices.
Class dac_cell2 (1):  Merged 2 parallel devices.
Class dac_cell2 (1):  Merged 1 series devices.
Subcircuit summary:
Circuit 1: dac_cell2                       |Circuit 2: dac_cell2                       
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_g5v0d10v5 (4)           |sky130_fd_pr__pfet_g5v0d10v5 (4)           
sky130_fd_pr__res_xhigh_po_0p69 (4->1)     |sky130_fd_pr__res_xhigh_po_0p69 (4->1)     
Number of devices: 5                       |Number of devices: 5                       
Number of nets: 9                          |Number of nets: 9                          
---------------------------------------------------------------------------------------
Resolving symmetries by property value.
Resolving symmetries by pin name.
Netlists match uniquely.

Subcircuit pins:
Circuit 1: dac_cell2                       |Circuit 2: dac_cell2                       
-------------------------------------------|-------------------------------------------
vgnd                                       |vgnd                                       
vbias                                      |vbias                                      
vsw                                        |vsw                                        
iout_n                                     |iout_n                                     
iout                                       |iout                                       
vsup                                       |vsup                                       
iref                                       |iref                                       
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes dac_cell2 and dac_cell2 are equivalent.

but for the subcell 5, the opamp we get:

Circuit 1: miel21_opamp                    |Circuit 2: miel21_opamp                    
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_g5v0d10v5 (3)           |sky130_fd_pr__pfet_g5v0d10v5 (26->3)       
sky130_fd_pr__nfet_g5v0d10v5 (5)           |sky130_fd_pr__nfet_g5v0d10v5 (14->5)       
sky130_fd_pr__res_xhigh_po_0p69 (3->1)     |sky130_fd_pr__res_xhigh_po_0p69 (3->1)     
sky130_fd_pr__cap_mim_m3_1 (1)             |sky130_fd_pr__cap_mim_m3_1 (1)             
Number of devices: 10                      |Number of devices: 10                      
Number of nets: 9                          |Number of nets: 9                          
---------------------------------------------------------------------------------------
Netlists match uniquely.

Subcircuit pins:
Circuit 1: miel21_opamp                    |Circuit 2: miel21_opamp                    
-------------------------------------------|-------------------------------------------
ground                                     |VSUBS **Mismatch**                         
inNeg                                      |inNeg                                      
inPos                                      |inPos                                      
outSingle                                  |outSingle                                  
power                                      |power                                      
---------------------------------------------------------------------------------------
Cell pin lists for miel21_opamp and miel21_opamp altered to match.
Device classes miel21_opamp and miel21_opamp are equivalent.

and then (omitting quite a bit of lines)

Circuit contains 12 nets, and 2 disconnected pins.

Circuit 1 contains 8 devices, Circuit 2 contains 8 devices.
Circuit 1 contains 12 nets,    Circuit 2 contains 12 nets.


Final result: 
Top level cell failed pin matching.

Logging to file "comp.out" disabled
LVS Done.

Again, note that individual LVS check for the opamp passes without any issues, circuits and netlists equivalent. And yet, here netgen shows

Mismatch

for that very same circuit. @Tim Edwards do you have an idea, maybe?

Here is the complete

comp.out

comp.out

I seem to be missing a layer... as with the above, I still get VSUBS in the extracted netlist, even though the m1 to the right goes directly to the VGND pin of the top cell.

That archive doesn't have the contact I just created above, I packed it before the attempt...

Ok, I've updated the layout of

miel21_opamp

, so just wandering now for the love of philosophy - what's the proper way of "refreshing" it in the top cell (and not close/open Magic)?

Also, how dangerous is this "altered to match" notification?