Hello. I have an warning when I make the spice file in magic. I run the command

extract all

. there are 1 warning. How can I know this warning? And, I ignore the warning and continue the LVS using netgen. The Netlist do not match. So, I check the comp.out file. There are many error like`Flattening unmatched subcell` . I guess the flatten is error. But flatten file can't check LVS. I have no idea to solve the error. What can I do for next step? I attatched images and file for your reference. I appriciate for your help.

@권용진학부생 How is

hgu_comp

different from

hgu_comp_flat

? Try (change layout top cell name).

lvs "hgu_comp.sch.spice hgu_comp" "hgu_comp_flat.spice hgu_comp_flat" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl

It is matching! But, It said

Top level cell failed pin matching

. So, I''ll check about pin. Thank you! Additionally, I have some questions Is that the same pin and port? In magic, there are two options at

Edit-text

Is it the problem to this failed matching? What is difference of hgu_comp and hgu_comp_flat? I think it is trival question. but I don't know what is different. I'm very appriciate for your help.

Check the

comp.out

file for pin differences.

Thank you. I think port is blue and pin is yellow. I did LVS using only pins. So, It has pin matching error. Thank you for your help.

Generally, ports and pins are the same thing. In an xschem schematic, these are placed as

ipin

,

opin

, or

iopin

. When a netlist for LVS is created, the pins/ports will be on the subckt definition line. These are signals that other circuits can use to connect to the circuit. You can also name nets in the schematic by placing a label on a net. These will netlist as internal nets that can not be accessed from outside the circuit. In the layout, there are corresponding ports/pins and text/labels. magic and klayout may handle these in a slightly different manner. In magic, you create either a pin/port or text/label. Both will extract a netlist with nets named with the corresponding text. However, only ports/pins will be in the subckt definition. In klayout, you’ll need to create a shape (generally a rectangle) on a layer with a pin purpose. This layer should be totally enclosed by the same layer with a drawing purpose. For example, to create a pin on an metal1 path, first create the metal1/drawing path. The switch to metal1/pin purpose layer and draw a rectangle within that metal1 shape. Finally, add the text on either the label layer or the pin layer (both are recognized when reading from gds). Note that on lower levels, magic can recognize connections to nets not defined as ports and will automatically add those to the port list. If these layers are not labeled, a unique name such as

a_12345_23456#

is given.

a

is the plane (in this case active/poly) and the 2 numbers are the x and y coordinates in magic data base units (DBU). (For sky130 and gf180, divide by 200 to get the coordinates in microns.). Netgen does not compare net names but will try to match port names. Port/pin name mismatches are generally an error that needs to be resolved. Also note that magic does not do permutation on logic gate inputs. For example, if a NAND gate has two inputs A and B, the connections must be the same in the layout and the schematic even though there is only a very slight difference in the actual output when the connections are reversed. This is a common type of port mismatch error.