GitHub
10/17/2023, 3:43 PMopen_pdks
. If sky130_fd_sc_hd.v
is read into Icarus Verilog without specifying a top module, it throws errors due to missing modules.
This PR removes the base instances from sky130_ef_sc_hd__fakediode_2
and sky130_ef_sc_hd__fill_12
and unifies some of the formatting. The standard cell libraries were built and read with iverilog, which is now happy:
iverilog primitives.v sky130_fd_sc_hd.v
RTimothyEdwards/open_pdks
GitHub Actions: Run (all)
GitHub Actions: Run (sky130_fd_sc_hvl)
GitHub Actions: Run (sky130_fd_sc_ls)
GitHub Actions: Run (sky130_fd_sc_ms)
GitHub Actions: Run (sky130_fd_sc_hs)
GitHub Actions: Run (sky130_fd_sc_hdll)
GitHub Actions: Run (sky130_fd_sc_hd)
✅ No checks have passed
0/7 successful checksGitHub
10/17/2023, 5:17 PM