#2019 Can not connect SRAM macros to the PDN Issue created by jacobhaehn Description I've followed the macro tutorials as closely as possible and have tried various different configurations, but OpenLane always seems to have issues connecting the SRAM22 macros (https://github.com/rahulk29/sram22_sky130_macros) to the PDN. I've been using the following settings (some details left out for brevity):

"EXTRA_LEFS": "...",
"EXTRA_GDS_FILES": "...",
"EXTRA_LIBS": "..."
"VERILOG_FILES_BLACKBOX": "..."
"MACRO_PLACEMENT_CFG": "dir::macro_placement.cfg"
"DESIGN_IS_CORE": true,
"FP_PDN_CORE_RING": true,
"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
"VDD_NETS": "VPWR",
"GND_NETS": "VGND",
"FP_PDN_MACRO_HOOKS": "system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched.bankedStore.cc_banks_0.cc_banks_0_ext.mem_0_0 VPWR VGND vdd vss ........."

Here the default VPWR and VGND nets are used and "hooked" to the vdd/vss pins on the SRAMS, but I get an error during PDN generation that all the SRAMs are not connected to the nets in the pdn.log. Same happens if I use vdd/vss as the net names. I have also tried creating 2 power nets, with

"VDD_NETS": "VPWR vdd", "GND_NETS": "VGND vss",

, and this successfully creates two power nets and passes PDN, connecting the SKY130 cells to VPWR/VGND, and connecting the macros to vdd/vss, but then fails at DRC when vdd and vss are shorted together for some reason. Either way, there's no reason to have 2 power nets here. Please let me know if you have any suggestions to try. Thanks! Expected Behavior OpenLane doesn't error out in PDN step and properly connects SRAM to the power grid. Environment report

Kernel: Linux v6.2.0-33-generic
Distribution: ubuntu 22.04
Python: v3.10.12 (OK)
Container Engine: docker v24.0.6 (OK)
OpenLane Git Version: 5215ea7cc01e5311086e995905492f0e8fe1ceb6
pip: INSTALLED
python-venv: INSTALLED
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PDK Version Verification Status: OK
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Git Log (Last 3 Commits)

5215ea7c 2023-09-20T15:53:26+03:00 Update `open_pdks` (#1992) - Mohamed Gaber -  (HEAD -> master, origin/master, origin/HEAD)
7e5a2e9f 2023-09-10T19:06:55+03:00 fix synthesis `chparam` issue (#1981) - Kareem Farid -  (tag: 2023.09.11)
0e8827eb 2023-09-10T19:04:45+03:00 `run_sta`: fix `-blackbox_check` not running when `-multi_corner` is not set (#1980) - Kareem Farid -  ()
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Git Remotes

origin	<https://github.com/The-OpenROAD-Project/OpenLane> (fetch)
origin	<https://github.com/The-OpenROAD-Project/OpenLane> (push)

Reproduction material For reference, unpackage the files with the following command:

cat sram_pdn_issue_reproducible.* | tar -xzvf -

sram_pdn_issue_reproducible.partaa.tar.gz sram_pdn_issue_reproducible.partab.tar.gz sram_pdn_issue_reproducible.partac.tar.gz sram_pdn_issue_reproducible.partad.tar.gz Relevant log output ``` 7-pdn.log (truncated repeated warnings to first 16 of each new instance): OpenROAD 0a6d0fd469bc674417036342994520ee2e0a2727 This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. [INFO]: Reading ODB at '/home/george/Documents/batfive/designs/batfive/openlane_src/runs/PDN_Issue/tmp/floorplan/6-tapcell.odb'… define_corners Typical read_liberty -corner Typical /home/george/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib read_liberty -corner Typical /home/george/Documents/batfive/sram22_sky130_macros/sramgen_sram_4096x32m8w8_replica_v1/sramgen_sram_4096x32m8w8_replica_v1_tt_025C_1v80.lib read_liberty -corner Typical /home/george/Documents/batfive/sram22_sky130_macros/sramgen_sram_4096x8m8w8_replica_v1/sramgen_sram_4096x8m8w8_replica_v1_tt_025C_1v80.lib read_liberty -corner Typical /home/george/Documents/batfive/sram22_sky130_macros/sramgen_sram_1024x32m8w8_replica_v1/sramgen_sram_1024x32m8w8_replica_v1_tt_025C_1v80.lib read_liberty -corner Typical /home/george/Documents/batfive/sram22_sky130_macros/sramgen_sram_512x32m4w8_replica_v1/sramgen_sram_512x32m4w8_replica_v1_tt_025C_1v80.lib read_liberty -corner Typical /home/george/Documents/batfive/sram22_sky130_macros/sramgen_sram_64x32m4w32_replica_v1/sramgen_sram_64x32m4w32_replica_v1_tt_025C_1v80.lib Using 1e-12 for capacitance... Using 1e+03 for resistance... Using 1e-09 for time... Using 1e+00 for voltage... Using 1e-03 for current... Using 1e-09 for power... Using 1e-06 for distance... Reading design constraints file at '/openlane/scripts/base.sdc'… [INFO]: Setting output delay to: 15.0 [INFO]: Setting input delay to: 15.0 [INFO]: Setting load to: 0.033442 [INFO]: Setting clock uncertainty to: 0.25 [INFO]: Setting clock transition to: 0.15 [INFO]: Setting timing derate to: 5.0 % [INFO PDN-0001] Inserting grid: stdcell_grid [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched.directory.cc_dir_0.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched.directory.cc_dir_1.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched.directory.cc_dir_2.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched.directory.cc_dir_3.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched.directory.cc_dir_4.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched.directory.cc_dir_5.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched.directory.cc_dir_6.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched.directory.cc_dir_7.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched_1.directory.cc_dir_0.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched_1.directory.cc_dir_1.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched_1.directory.cc_dir_2.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched_1.directory.cc_dir_3.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched_1.directory.cc_dir_4.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched_1.directory.cc_dir_5.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched_1.directory.cc_dir_6.cc_dir_0_ext.mem_0_0 [INFO PDN-0001] Inserting grid: macro - system.subsystem_l2_wrapper.l2.inclusive_cache_bank_sched_1.directory.cc_dir_7.cc_dir_0_ext.mem_0_0 ....... [WARNING PDN-0110] No via inserted between met4 and met5 at (3324.5400, 2787.2700) - (3326.1400, 2788.2400) on VGND [WARNING PDN-0110] No via inserted between met4 and met5 at (3821.3400, 2787.2700) - (3822.9400, 2788.2400) on VGND [WARNING PDN-0110] No via inserted between met4 and met5 at (6677.9400, 2787.2700) - (6679.5400, 2788.2400) on VGND [INFO PSM-0076] Setting metal node density to be standard cell height times 5. [INFO PSM-0031] Number of PDN nodes on net VPWR = 922556. [INFO PSM-0064] Number of vo… The-OpenROAD-Project/OpenLane