Its causing trouble later on because we have defined all 8 nets in "VDD_NETS" and "GND_NETS" in the config.json so openlane falls down at Step 34 (IR drop) with this error:

Do you have this line in your

config.json

file? (See

openlane/user_project_wrapper/config.json

for an example that includes all 8 power pins).

"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",

I didn't have it in there, but including it doesn't seem to make a difference - PDN still only makes vccd1 and vssd1 at Step 6. I have even tried commenting them out in the verilog altogether, but they are both still made! Its like its got a pre-defined setting somewhere to make those 2 nets only, and I don't know where that might be?

Just some suggestions. No experience with what would work. 1. Does the

verilog/gl/TOP_digital.v

file have all the power/ground nets defined? 2. Have you tried adding a power ring? The unconnected power/ground nets may be automatically deleted. Here’s an example from

user_project_wrapper

.

"FP_PDN_CORE_RING"                : "1",
    "FP_PDN_CORE_RING_HOFFSET"        : "14",
    "FP_PDN_CORE_RING_HSPACING"       : "1.7",
    "FP_PDN_CORE_RING_HWIDTH"         : "3.1",
    "FP_PDN_CORE_RING_VOFFSET"        : "14",
    "FP_PDN_CORE_RING_VSPACING"       : "1.7",
    "FP_PDN_CORE_RING_VWIDTH"         : "3.1",

Thank you @Mitch Bailey, will look into those suggestions this week :)