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<https://github.com/The-OpenROAD-Project/OpenLane/issues/2015|#2015 error generating PDN for the design>
Issue created by <https://github.com/Pa1mantri|Pa1mantri>
*Description*

I have used FP_PDN_MACRO_HOOKS variable for connecting macros to the power grid. One of the macro instances (cntlr) is not being recognized. I found on the internet to use verilog_files_blackbox variable . If it is, can you help me what all the files that are needed to include in that variable. I have .lef,.gds,.lib files of memory(sram) but none of these files for the controller module. If i remove the cntlr instance completely it results in LVS errors at the end.

*Expected Behavior*

successful flow of the design without lvs errors. Thank you.

*Environment report*

```
This makes it difficult to rule out issues with your
environment.

Unless instructed specifically to do so, please run this command
outside the OpenLane container.
---

Kernel: Linux v6.2.0-32-generic
Distribution: centos 7
Python: v3.6.8 (OK)
OpenLane Git Version: 00caae2b3186bb6b24a0b7db7ee1a6f056ad1702
pip: INSTALLED
python-venv: INSTALLED
---
PDK Version Verification Status: OK
---
Git Log (Last 3 Commits)

00caae2b 2023-08-22T19:35:09+03:00 Update PDK + Restore `RC_LAYER` variables (#1932) - Kareem Farid -  (HEAD -&gt; master, tag: 2023.08.23, origin/master, origin/HEAD)
eaa6680c 2023-08-22T19:12:10+03:00 `run_designs.py`: Fix `mkdirp` not being called in some scenarios (#1945) - UMW -  ()
17559fa5 2023-08-22T18:54:25+03:00 CI Tweaks (#1951) - Mohamed Gaber -  ()
---
Git Remotes

origin	<https://github.com/The-OpenROAD-Project/OpenLane> (fetch)
origin	<https://github.com/The-OpenROAD-Project/OpenLane> (push)
```

*Reproduction material*

<https://github.com/The-OpenROAD-Project/OpenLane/files/12866966/issue.tar.gz|issue.tar.gz>

*Relevant log output*

```
OpenROAD 0cfb9a45bfb256c9af1a0500d4c97da0f145f54f 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO]: Reading ODB at '/openlane/designs/vsdmemsoc/runs/RUN_2023.10.11_08.29.14/tmp/floorplan/6-tapcell.odb'…
define_corners Typical
read_liberty -corner Typical /home/pa1mantri/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_liberty -corner Typical /openlane/designs/vsdmemsoc/src/macros/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
Using 1e-12 for capacitance...
Using 1e+03 for resistance...
Using 1e-09 for time...
Using 1e+00 for voltage...
Using 1e-03 for current...
Using 1e-09 for power...
Using 1e-06 for distance...
Reading design constraints file at '/openlane/designs/vsdmemsoc/runs/RUN_2023.10.11_08.29.14/tmp/floorplan/3-initial_fp.sdc'…
No regex match found for cntlr defined in FP_PDN_MACRO_HOOKS
```
<https://github.com/The-OpenROAD-Project/OpenLane|The-OpenROAD-Project/OpenLane>