Hi designers, I am currently working on a mixed-s...
# analog-design
f
Hi designers, I am currently working on a mixed-signal simulation involving a test bench with various components, including a SAR ADC, a current sensor, a digital control module written in Verilog, and a buck converter. However, I’m encountering a significant simulation speed issue as it progresses very slowly, simulating only 500ps per day. To provide some context, I have already allocated 4 CPUs and set 4 num_threads to improve simulation performance, but it still remains sluggish. I would greatly appreciate any insights or suggestions from the community on how to expedite this simulation. Is it typically feasible to achieve faster simulation times for this type of mixed-signal setup, or should I be prepared for longer simulation durations? Any advice or recommendations on optimizing my simulation setup would be highly valuable. Thank you in advance for your expertise and assistance.
t
What simulator are you using? If you are using ngspice, then converting the digital control to xspice format will greatly speed up the simulation.
If you care about the analog characteristics but not so much about the exact timing characteristics of the digital, then the script
spi2xspice.py
from qflow (https://github.com/RTimothyEdwards/qflow) will convert the digital block(s) to xspice format.
f
Yes I'm using ngspice. Do you have a guide to convert in xspice?
t
Usage:
Copy code
spi2xspice.py <liberty file> <input spice> <output spice>
You will need a liberty file from the PDK for the standard cell set used by the digital block. The output of
spi2xspice.py
is a
.subckt
block that is an exact replacement for the original
.subckt
but using xspice primitives instead of analog components.
f
Ok, but now I am not using analog components fro simulate the digital core but "hdl library" of ngspice: https://sourceforge.net/u/glennramalho/ngspice/ci/master/tree/src/xspice/icm/digital/d_hdl/
I think is more faster of xspice primitive... or not?
a
Xspice is 100x faster at least in most scenarios.
I would take @Tim Edwards advise.
Thanks @Tim Edwards for sharing. Amazing work btw, we didn't know that this existed and built something similar in python internally.
t
@Filippo: If you are using d_hdl, thenn you are using xspice.
r
How did I get dragged into this?
t
@Russell Friesenhahn :Sorry. Slack problems + a very slow internet connection. How I clicked on "Filippo" and it came up with your name. . . I have absolutely no idea. Presumably caused by the seconds-long lag I was experiencing.
👍 1
f
@Tim Edwards: Ok so, I can't speed up more my simulation?
t
@Filippo: It sounds like you have probably optimized it as well as it can be optimized.
f
Okay thanks!