Hi @Matt Venn Can please explain how did you controlled the following signals in your wishbone demo..?

input wb_rst_i,

input wbs_stb_i,

input wbs_cyc_i,

input wbs_we_i,

input [3:0] wbs_sel_i,

input [31:0] wbs_dat_i,

input [31:0] wbs_adr_i,

take a look at the verilog file that drives them, that should explain