Hi does this csv file: https://github.com/google/skywater-pdk-libs-sky130_fd_pr/blob/f62031a1be9aefe902d6[…]d6f59b57627436/cells/pfet_01v8/sky130_fd_pr__pfet_01v8.bins.csv indicate the transistor sizing available for fabrication or does it also include for simulation? If I use any other sizing than this list ngspice successfully runs without any error of invalid sizing

There are some model files that are binned only around the characterized sizes. But if you run a corner simulation using the corner models, the model lmin/lmax/wmin/wmax limits have been increased so that they span a continuous range, and you can simulate for any L and W. There is no prohibition against manufacturing with any L or W. However, we have some concerns about the validity of the device models as you move away from the characterized L and W values, especially at the boundaries halfway in between, where there are actual discontinuities in some of the parameters. There is a set of "continuous" models that supposedly corrects the issue of the boundary discontinuities. However, those models have been tested (lightly) and they do not seem to appreciably change the models. Probably because they used the same base measurement data. And yes, the CSV file has the L and W of the devices that were measured for characterization, so you can use that as a guide for device sizing if you want to make sure you don't run into any issues caused by being somewhere in interpolated characterization space.

thanks @Tim Edwards that was helpful