Hi, I have an issue regarding setting constraints with hierarchical paths. I believe the issue is caused by Yosys flattening the netlist and not regenerating the SDC constraints with the updated paths. This is then causing the constraints to not be recognized as many of the signals were renamed and the hierarchy was lost. Not flattening the netlist doesn't fix the issue either. By default Yosys doesn't seem to have the feature to rewrite sdc constraints, I've tried using the following plugin: sdc-plugin for Yosys, which adds support for read_sdc and write_sdc, but the generated SDC constraints are also based on the pre-synthesis RTL (not compatible with the post synthesis netlist). This is causing issues in the flow since STA is not able to recognize the timing constraints. Adjusting the constraints manually to match the post-synthesis netlist seems to work, however, the netlist is quite large and there are many SDC constraints so that is not really feasible for my project. Is there a solution to this other than adjusting the SDC constraints according to the post synthesis netlist?

This is a real problem with yosys. I don't know what the plugin does but if it uses the pre-synth names then it sounds like a no-op.

Seems like the plugin doesn't actually add this feature, I added the plugin and installed separately. But it's not regenerating the constraints (from pre-syn to post-syn) names. It seems that doesn't solve the issue. Just to confirm, Yosys doesn't support this by default right?

not to my knowledge

Thank you very much