I understood that in circuit design with standard cells as building blocks, the cells are placed in parallel rows. Also in each row, cells providing logic functions (and, or etc...) are interleaved with tap and decap cells. Tap and decap are used to guard the circuit against latch-up and vdd drop. So in each row there is a tap every X logic cells and a decap every Y logic cells. X and Y are process depended. If my understanding is correct, what are X e Y for Skywater standard cells ?

The tap cells have to be placed at most a certain distance (15µm, for example) from the transistors in the same island. How many cells is that depends on the width of the cells (a NOT will be much narrower than a four input NAND gate, for example). If this rule is violated then the resistance between the tap and a transistor might be too high for it to work properly

@Giuseppe Quaratino Here are a couple screen shots to go along with @Jecel Assumpção Jr explanation.

Mitch Bailey, in the screenshot it is reported 26. May I ask where this number does come from ? I'm still searching on internet but I didn't find anything.

While we normally show mosfets with three terminals (source, drain and gate) they actually have a fourth one (substrate). For most circuits, specially CMOS logic gates, the substrate of the n transistors is connected to ground and the substrate of the p transistors to Vdd. That connection happens with the tap cells which sets the substrate voltage for that whole island ("well" is the correct term). The problem is that the doped silicon that makes up the well has a certain resistance and the the further away a particular transistor is from the nearest tap cell the less that its substrate is actually at ground (or Vdd) and the worse it will perform. As the picture shows, placing taps every 26µm and staggering them ensures no transistor is ever more than 7µm away from a tap, which in turn ensures that the substrate is less than X mV away from ground (or Vdd). To get the 7µm number you need to know what X we want and the resistance of the N and P wells.

@Guiseppe Maugeri Maybe from

FP_TAP_HORIZONTAL_HALO

and

FP_TAP_V_HALO

Ok I understood. I answer to myself: I downloaded a GDS file regarding a project made with OpenLane. I opened it with Klayout. Taps are placed every 26µm. This seems to be the correct number for Skywater130 process.