Hi! I want to create a verilog-A module (say a simple inverter). I want the output to not change for changes of very short durations in the input. Let's say the input goes from 1 to 0 for only 10fs, I do not want the output to go from 0 to 1 for these short duration fluctations in the input. Can anyone help me with any resources on how to model this in verilog-A?

You could make it work as close as possible an an actual inverter. Make an inner node which buffers the input to an RC lowpass filter. Then, the inner voltage should be the input of an comparator. You could replace the RC by and GmC filter, which is a better model of the inverter

Thanks Luis, I shall try that. I was wondering if there are any filters (like transition), which when given the appropriate arguments can do this automatically.

Something you could do is a first stage veriloga inverter with a large transition time, followed by a histeresis comparator. I can't find the veriloga examples, but once I've found them in design-reuse.com . Any signal with faster than the transition time to reach the comparator threshold wouldn't flip the output.