hello all, i am trying to design this circuit with big transistors and i am supposed to use fingers to represent the big transistors. but still having issues. could you please help me figuring out the issue and help me to pass lvs. is there any alternative way to handle this issue in magic? thank you

@Md. Sajjad Hossain Not sure what problem is occurring during LVS because you didn’t include the lvs result file. You might try creating a schematic netlist with the top level as a subckt.

Simulation

->

LVS netlist: Top level is a .subckt

before netlisting.