Ports don't appear in LVS export from hierarchical...
# magicg
Giuseppe Maugeri
09/21/2023, 8:25 AMI have a doubt regarding the right way to set ports in a cell made with a hierarchical design.
I have an AND cell made from a NAND cell plus an INVERTER cell.
In the top level I connected the NAND output to the inverter input and made three ports: A and B as inputs in correspondence of NAND inputs
and a OUT port in correspondence of the inverter output.
I exported this design with the commands:
1) export all
2) ext2spice lvs
3) ext2spice -d
My problem is I don't see any port in the AND subcircuit made from the layout.
My questions:
1) What I have to do in order to make appear the ports in the subcircuit ?
2) Have I to put something else in the top level, example metal and contact, in correspondence of port label in order
to make appear the port ?
t
Tim Edwards
09/21/2023, 2:10 PMPosting a layout or screenshot (preferably layout) would help. However, the simple answer is: Yes, you need to declare ports specifically. Works best if you just use the text GUI from "Edit->Text..." and then check the box that says "Port: enable". But if you have a layout that already has non-port labels, then just turn each one into a port by putting the cursor box around the label area and typing the command
port makeg
Giuseppe Maugeri
09/21/2023, 3:43 PMI made a label and then link a port with the command: port make <index>.
Giuseppe Maugeri
09/21/2023, 3:46 PMIf I later check selecting the label and using the command : port index
Giuseppe Maugeri
09/21/2023, 3:46 PMI find the correct port index.
Giuseppe Maugeri
09/21/2023, 3:46 PMSo port seems to be created.
t
Tim Edwards
09/21/2023, 3:47 PMPost a layout.
g
Giuseppe Maugeri
09/21/2023, 3:47 PMok give me a while ...
Giuseppe Maugeri
09/21/2023, 3:52 PMHere another layout more complex (4 Bit P-G network) with the same problem.
Giuseppe Maugeri
09/21/2023, 3:52 PM1.png
Giuseppe Maugeri
09/21/2023, 3:53 PMLook at GND port on top layer.
Giuseppe Maugeri
09/21/2023, 3:53 PM1_mod.png
Giuseppe Maugeri
09/21/2023, 3:54 PMThis is the bottom layer with ground track.
Giuseppe Maugeri
09/21/2023, 3:54 PM2.png
t
Tim Edwards
09/21/2023, 6:21 PMWhen I say "post a layout", I mean "post a layout", not "post a screenshot of a layout".
g
Giuseppe Maugeri
09/21/2023, 7:45 PMHere the layout the screenshots are referring to.
t
Tim Edwards
09/21/2023, 10:11 PMThe problem is that you have labels "VDD" and "GND", but there is no material in the top level cell under the labels, so they are not attached to anything. If you want them to be attached to metal1 without any material underneath in the same cell, then you need to select the "sticky" checkbox in the text helper dialog window, and enter "metal1" in the entry box after "Attach to layer:"
Tim Edwards
09/21/2023, 10:13 PMI think only the "GND" label is incorrect.
g
Giuseppe Maugeri
09/22/2023, 9:01 PMI solved my issue. Thanks for the help.
i
IAN ERIK CONCEPCION ALVARADO
01/18/2024, 9:58 PM Copy code
Hello, I am doing something similar, the simulation in xschem and the one in Magic theoretically have to work well but in magic there are many details from the thickness of the wiring the way to put the labels the way the cables cross, sometimes parasitic capacities are generated after the LVS there is one last test that must be done: the extraction of parasitic capabilities is carried out and at the end a Post-layout simulation Create a test harness around the netlist with parasitic which is a .sp file
<http://web02.gonzaga.edu/faculty/talarico/vlsi/13_magic_inverter_sky130.pdf> In that document the procedure is explained, I hope it helps you34 Views