mehdi
09/20/2023, 3:40 PMGabriel Maranhão
09/21/2023, 6:15 PManalog_leak_pads.sch
is a test to plot the leak current of the ESD (asig5V IO cel) circuit using the extracted view provided to us gf180mcu_fd_io__asig_5p0_extracted
. That is why we are creating another PAD with lower or without ESD circuits (none of them will connect to gate).
2. The second schematic inverter_pads_dc.sch
is a DC simulation of a simple inverter. Here I included the __cor
__asig
__dvdd
__dvss
__fill
cells to test all of them together, and see if they influence on something, since they add a lot of passive components. Here we are not using extracted views.
3. The third schematic inverter_pads_tran.sch
is a transient simulation of the same inverter. Adding the same IO cells of the previous schematic. I added some text indicating the problem, the transient simulation hardly works with all cells, and with the __cor
cell it does not work at all. Here we are not using extracted views.
Another point:
In parallel I'm trying to run PEX on each of the IO cells, and also on the PAD_RING (Michigan) that was provided. I have a script run_ex.sh
to run PEX on magic that was fixed by @Tim Edwards and I tested it on some simple layouts, made some post-layout simulation.
BUT the extraction of the IO cells are not working, neither for the PAD_RING, it seems to me that the extraction is not identifying the PIN/Labels names, and also none resistor is added after PEX, only Caps on "wrong" labels. So we are unable to test our circuits with the extracted view of the PADS, I know that they were manufactured and tested, but it would be good to test them together with our analog blocks, also because we are creating another "new" PAD.
Attached to this conversation are the files related to the PEX (PAD_RING, my script and an initial analog pad without ESD).Yukidamayaki
09/22/2023, 2:38 PMGabriel Maranhão
09/22/2023, 6:25 PMgf180mcu_fd_io__asig_5p0
so I could compare the results with the one that you provide for us. The PEX "worked", and the .spice
file created is attached.
But, when comparing with the one on the repo (https://github.com/idea-fasoc/openfasoc-tapeouts/tree/main/gf180mcu_padframe/tb) There are a lot of differences, mainly on the number of capacitors extracted. Also, the simulation using each one has big different results.mehdi
09/22/2023, 6:31 PMGabriel Maranhão
09/22/2023, 7:40 PMGabriel Maranhão
09/22/2023, 7:58 PMTim Edwards
09/23/2023, 1:28 PMTim Edwards
09/23/2023, 2:26 PMR67708 ASIG5V.n8700 ASIG5V 7.60079
R67709 ASIG5V.n7465 ASIG5V 7.59795
R67710 ASIG5V.n8261 ASIG5V 7.5976
R67711 ASIG5V.n7511 ASIG5V 7.59689
R67712 ASIG5V.n7263 ASIG5V 7.59689
R67713 ASIG5V.n7571 ASIG5V 7.59512
R67714 ASIG5V.n7072 ASIG5V 7.59512
R67715 ASIG5V ASIG5V.n13839 7.59512
These are the 8 metal2 fingers running from the pad to the core; the resistance network has been broken into pieces and these are the unbroken lines running from the last ESD diode connection to the core pin position. The metal 2 lines are 2.5um wide and 215um long. So each one is about 86 squares, and at 90 milliohms per square, that comes to about 7.7 ohms, which agrees with the output above. Beyond that, the signal pad resistance network is broken up into hundreds of contacts and becomes impossible to eyeball.
Something has gone completely wonky with the device extraction, though. The output from magic for the moscaps is
X35 DVDD.t43 DVSS.t0 cap_nmos_06v0 c_width=75u c_length=75u
There are 36 extracted devices, which is right, but they are being given W and L of 75um when the devices are actually 15um x 15um.
Likewise the diodes are output as:
D11 DVSS.t37 ASIG5V.t7 diode_nd2ps_06v0 pj=0.53m area=3.75n
Which again is the right number of diodes but the area and perimeter numbers are off. And the amount by which they are off is exactly 5 for length and 25 for area.
I did a basic extraction of the gf180mcu_fd_io__asig_5p0
cell and the device lengths, widths, areas, and perimeters all come out correctly.
I am currently running a parasitic extraction of the same file to see how it compares to yours, so I can figure out if it's an issue with annotating the basic extraction with parasitics, or if it is some setup issue on your end.
At any rate, I am quite sure that the simulation results are dominated by the diode and moscap devices, not by the metal parasitics.Tim Edwards
09/23/2023, 5:06 PMextresist
. I investigated and found that it was spending all of its time running an area search on a zero-sized area. So I fixed that, and the run-time of extresist
went from "interminable" (I didn't wait for it to finish, but it had been running several hours) to several seconds. The patched version of magic is 8.3.432.Tim Edwards
09/24/2023, 5:01 PMGabriel Maranhão
09/25/2023, 6:31 PMgf180mcu_fd_io__asig_5p0_extracted.spice
Is the PEX file using closed-source tools
First of all I copy the Cell gf180mcu_fd_io__asig_5p0
from RING_PAD.gds
to another .gds file to make it the TOP CELL, with the same name as the gds file, so I create the gf180mcu_fd_io__asig_5p0.gds
with a solo cell: gf180mcu_fd_io__asig_5p0
. Running my script run_ex.sh
(uploaded on this thread ) I got errors regarding the labels, probably magic does not recognized those labels as ports and I got a .spice file with a .subckt without any node.
After that I placed each PORT manually on magic Edit->Text ... -> Port -> Enable :
Type ASIG5V to each 8 metal2 terminals, and also added the DVDD, DVSS, VDD and VSS to the metal5 rail on the top of the cell. With this I continued to run the script (direct on terminal, line by line) and got that final .spice file.
magic version: 8.3.424
GF180mcuC _version_: 1341f54f5ce0c4955326297f235e4ace1eb6d419 (2023.08.27)
I'm going to update magic, PDK, and repeat the same procedure, with that, I will get the output and send to you, doing this right now. BTW, this error on W and L could be related to grid size differences for klayout and magic ?
FYI, I made a schematic that uses both PEX files, closed-tool(repo link) and open-tool (the one that you gave to us). My schematic just get the leakage of the PAD, from a ideal current source that I placed going into the PAD sub-circuit. Attached is the results using each one of the .spice PEX files.
Leak current is lower ~5x for open-source tools.Tim Edwards
09/25/2023, 10:07 PMGabriel Maranhão
09/25/2023, 10:20 PMgf180mcu_fd_io__asig_5p0_gab.spice
so we don't get confused with so many files.
Thank you a lot for your assistance on this process. Feel free to request anything.Tim Edwards
09/26/2023, 2:06 AMrASIG5V/141 ASIG5V:3013 ASIG5V:1321 8.9712
rASIG5V/167 ASIG5V:2995 ASIG5V:1305 8.96285
rASIG5V/63 ASIG5V:3067 ASIG5V:1369 9.27884
rASIG5V/89 ASIG5V:3049 ASIG5V:1353 9.41378
rASIG5V/115 ASIG5V:3031 ASIG5V:1337 9.12149
rASIG5V/193 ASIG5V:2977 ASIG5V:1289 9.11067
rASIG5V/219 ASIG5V:2959 ASIG5V:1273 9.39452
rASIG5V/245 ASIG5V:2941 ASIG5V:1257 9.21806
which are a bit bigger than what I calculated (more like 8 ohms) but certainly not 5x off. Following one of those paths in the netlist, the next component is a 0.225 ohm resistor, which matches what I would expect from condensing down the 20-via array (at 4.5 ohms per via) from metal 2 to metal 1.
After that it gets much harder to figure out how the extraction has divided up the diffusion contacts under the metal 1.
The network extracted from magic is harder to figure out because it is not condensing down the via arrays (normally it would do this but the via rules prohibit magic from merging together the contacts on GDS read, resulting in individual vias, which then get extracted individually).
I will spend some time trying to figure out whether magic's extraction of the resistance network down to a diode is sensible or not.Tim Edwards
09/28/2023, 12:33 AMGabriel Maranhão
09/28/2023, 1:23 AMTim Edwards
09/28/2023, 10:01 PMTim Edwards
09/29/2023, 9:48 PMGabriel Maranhão
10/02/2023, 4:09 PMTim Edwards
10/02/2023, 5:35 PMGabriel Maranhão
10/03/2023, 12:37 AMTim Edwards
10/03/2023, 12:48 AMGabriel Maranhão
10/04/2023, 6:53 PMpulse(0 3.3 50p 50p 50p 1u 5u)
. A "Slow" signal to give time to charge the capacitors. Faster signals do not work even for the analog IO cell schematic
1. The schematic results are as expected for a inverter;
2. The closed PEX results are inconclusive, if I add it to the circuit the transient simulation abort (time step too small, tried a lot of things to fix it but did not work);
3. The magic PEX results shows a output signal but it goes from 0V to ~0.7V and not 3.3V. And I thing that this is not a problem regarding the time to charge the capacitors, the high value just sits at ~0.7V (image attached, blue signal).Tim Edwards
10/05/2023, 7:14 PMgf180mcu_fd_io__asig_5p0
for both the schematic-extracted and magic layout-extracted cells. Either one of them is a different name, or you have colliding cell names in the netlist. The pin order is different, which probably explains the simulation behavior.Gabriel Maranhão
10/19/2023, 8:15 PMTim Edwards
10/19/2023, 9:09 PM.option RELTOL=1e-2
Convergence issues and solving them are a bit of a mystery. I have not (yet) found a set of options that will get the closed-source netlist to simulate.
This page: https://efabless.com/kb-articles/overcoming-spice-convergence-issues is something we wrote up at Efabless some years ago for helping users through issues with convergence on ngspice. ngspice is not as good as the commercial tools at automatically solving convergence problems, and the larger the circuit gets, the more likely that some manual intervention will be needed.Gabriel Maranhão
10/20/2023, 6:45 PMTim Edwards
10/20/2023, 7:00 PMTim Edwards
10/20/2023, 7:04 PM