#1972 Error DRT-0218 Guide is not connected to design Issue created by jchin2 Description Making blackbox of layout that has dnwell and nwell guard rings. Goal to have openlane recognize, route and connect to the blackbox. Openlane seemingly can't find the pins. Initially started with pins within the prboundary and then moved them outside plus elongating the pins. Omitted

FP_PDN_HOOK

to see that it doesn't make a difference. Relevant files is included in the current_state_09042023.zip folder. Expected Behavior Openlane to recognize, route and connect the pins to the blackboxed macro layout. Environment report

Kernel: Linux v6.2.0-31-generic
Distribution: ubuntu 22.04
Python: v3.11.3 (OK)
Container Engine: docker v24.0.5 (OK)
OpenLane Git Version: d054702b2cce04761cc2bc598f6b95c9d8ca7c6c
pip: INSTALLED
python-venv: INSTALLED
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PDK Version Verification Status: FAILED
/home/jchin2/sky130/openlane_src/pdks/sky130A not found.
Traceback (most recent call last):
  File "/home/jchin2/sky130/openlane_src/dependencies/verify_versions.py", line 76, in verify_versions
    raise Exception(f"{pdk_dir} not found.")
Exception: /home/jchin2/sky130/openlane_src/pdks/sky130A not found.

Failed to verify sky130A.
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Git Log (Last 3 Commits)

d054702 2023-07-19T16:09:15+03:00 remove `unset_propagated_clock` (#1908) - passant5 -  (grafted, HEAD, tag: 2023.07.19)
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Git Remotes

origin	<https://github.com/The-OpenROAD-Project/OpenLane> (fetch)
origin	<https://github.com/The-OpenROAD-Project/OpenLane> (push)

Reproduction material issue_reproducible.zip current_state_09042023.zip Relevant log output ``` (base) jchin2@short-simple:~/sky130/caravel_user_project_analog$ make blackbox_test_3 cd openlane && make blackbox_test_3 make[1]: Entering directory '/home/jchin2/sky130/caravel_user_project_analog/openlane' # blackbox_test_3 mkdir -p ./blackbox_test_3/runs/23_09_04_07_10 rm -rf ./blackbox_test_3/runs/blackbox_test_3 ln -s $(realpath ./blackbox_test_3/runs/23_09_04_07_10) ./blackbox_test_3/runs/blackbox_test_3 docker run -it -v $(realpath /home/jchin2/sky130/caravel_user_project_analog/openlane/..):$(realpath /home/jchin2/sky130/caravel_user_project_analog/openlane/..) -v /home/jchin2/sky130/pdks:/pdk -v /home/jchin2/sky130/caravel:/home/jchin2/sky130/caravel -v /home/jchin2/sky130/openlane_src:/openlane -e PDK_ROOT=/pdk -e PDK=sky130A -e MISMATCHES_OK=1 -e CARAVEL_ROOT=/home/jchin2/sky130/caravel -e OPENLANE_RUN_TAG=23_09_04_07_10 -u 1000:1000 \ efabless/current-local-amd64 sh -c "flow.tcl -design $(realpath ./blackbox_test_3) -save_path $(realpath ..) -save -tag 23_09_04_07_10 -overwrite -ignore_mismatches" OpenLane d054702b2cce04761cc2bc598f6b95c9d8ca7c6c All rights reserved. (c) 2020-2022 Efabless Corporation and contributors. Available under the Apache License, version 2.0. See the LICENSE file for more details. [INFO]: Using configuration in '../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/config.json'... [INFO]: PDK Root: /pdk [INFO]: Process Design Kit: sky130A [INFO]: Standard Cell Library: sky130_fd_sc_hd [INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd [INFO]: Run Directory: /home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10 [INFO]: Saving runtime environment... [INFO]: Preparing LEF files for the nom corner... [INFO]: Preparing LEF files for the min corner... [INFO]: Preparing LEF files for the max corner... [INFO]: Running linter (Verilator) (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/synthesis/linter.log)... [INFO]: 0 errors found by linter [WARNING]: 9 warnings found by linter [STEP 1] [INFO]: Running Synthesis (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/synthesis/1-synthesis.log)... [STEP 2] [INFO]: Running Single-Corner Static Timing Analysis (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/synthesis/2-sta.log)... [STEP 3] [INFO]: Running Initial Floorplanning (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/floorplan/3-initial_fp.log)... [INFO]: Floorplanned with width 288.88 and height 225.76. [STEP 4] [INFO]: Running IO Placement... [STEP 5] [INFO]: Performing Manual Macro Placement (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/placement/5-macro_placement.log)... [STEP 6] [INFO]: Running Tap/Decap Insertion (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/floorplan/6-tap.log)... [INFO]: Power planning with power {VPWR} and ground {VGND}... [STEP 7] [INFO]: Generating PDN (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/floorplan/7-pdn.log)... [STEP 8] [INFO]: Running Global Placement (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/placement/8-global.log)... [STEP 9] [INFO]: Running Single-Corner Static Timing Analysis (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/placement/9-gpl_sta.log)... [STEP 10] [INFO]: Running Placement Resizer Design Optimizations (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/placement/10-resizer.log)... [STEP 11] [INFO]: Running Detailed Placement (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/placement/11-detailed.log)... [STEP 12] [INFO]: Running Single-Corner Static Timing Analysis (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/placement/12-dpl_sta.log)... [STEP 13] [INFO]: Running Clock Tree Synthesis (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/cts/13-cts.log)... [STEP 14] [INFO]: Running Single-Corner Static Timing Analysis (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/cts/14-cts_sta.log)... [STEP 15] [INFO]: Running Placement Resizer Timing Optimizations (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/cts/15-resizer.log)... [STEP 16] [INFO]: Running Global Routing Resizer Design Optimizations (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/routing/16-resizer_design.log)... [STEP 17] [INFO]: Running Single-Corner Static Timing Analysis (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/routing/17-rsz_design_sta.log)... [STEP 18] [INFO]: Running Global Routing Resizer Timing Optimizations (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/routing/18-resizer_timing.log)... [STEP 19] [INFO]: Running Single-Corner Static Timing Analysis (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/routing/19-rsz_timing_sta.log)... [STEP 20] [INFO]: Running Global Routing (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/routing/20-global.log)... [INFO]: Starting OpenROAD Antenna Repair Iterations... [STEP 21] [INFO]: Writing Verilog (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/routing/20-global_write_netlist.log)... [STEP 22] [INFO]: Running Single-Corner Static Timing Analysis (log: ../home/jchin2/sky130/caravel_user_project_analog/openlane/blackbox_test_3/runs/23_09_04_07_10/logs/routing/22-grt_sta.log)..… The-OpenROAD-Project/OpenLane