Hey guys. This is likely a very basic question. I have recently completed and open source my design prototype: https://github.com/lob-software/xoc I have further tested the verilog on my FPGA board, Arty 100A. Can someone provide me some pointers as to what is involved in getting an ASIC made for my design? Highly appreciate any help.

If you want to integrate your design into the caravel framework, follow these instructions. 1. Drop your verilog files into

verilog/rtl

, 2. modify

verilog/rtl/user_proj_example.v

to access your modules and connect to appropriate io signals, 3.

make user_proj_example

4.

make user_project_wrapper

submit your design

thank you @Mitch Bailey

You may also want to have a look at TinyTapeout. It's a project to aggregate lots of small digital designs into a single chip to make the fabrication accessible from a hobbyist budget. Your design looks reasonably small to qualify.

@Mitch Bailey I am having trouble mapping the pins from my FPGA board to the pins that I have available in the caravel project. What I mean is best demonstrated. I have a set of constraints, which defines pins that I use on the FPGA board:

set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

# Clock and Reset
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports {clock}]
create_clock -period 10.0 [get_ports {clock}]
set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { reset }]

# UART
set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { io_uartRx }];
set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { io_uartTx }];

However I cannot quite match those to pins specified in `caravel_user_project/verilog/rtl/user_defines.v`:

`default_nettype none

`ifndef __USER_DEFINES_H
// User GPIO initial configuration parameters
`define __USER_DEFINES_H

// deliberately erroneous placeholder value; user required to config GPIO's to other
`define GPIO_MODE_INVALID                  13'hXXXX

// Authoritive source of these MODE defs is: caravel/verilog/rtl/user_defines.v
// Useful GPIO mode values.  These match the names used in defs.h.
//
`define GPIO_MODE_MGMT_STD_INPUT_NOPULL    13'h0403
`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN  13'h0c01
`define GPIO_MODE_MGMT_STD_INPUT_PULLUP    13'h0801
`define GPIO_MODE_MGMT_STD_OUTPUT          13'h1809
`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL   13'h1801
`define GPIO_MODE_MGMT_STD_ANALOG          13'h000b

`define GPIO_MODE_USER_STD_INPUT_NOPULL    13'h0402
`define GPIO_MODE_USER_STD_INPUT_PULLDOWN  13'h0c00
`define GPIO_MODE_USER_STD_INPUT_PULLUP    13'h0800
`define GPIO_MODE_USER_STD_OUTPUT          13'h1808
`define GPIO_MODE_USER_STD_BIDIRECTIONAL   13'h1800
`define GPIO_MODE_USER_STD_OUT_MONITORED   13'h1802
`define GPIO_MODE_USER_STD_ANALOG          13'h000a

// The power-on configuration for GPIO 0 to 4 is fixed and cannot be
// modified (allowing the SPI and debug to always be accessible unless
// overridden by a flash program).

// The values below can be any of the standard types defined above,
// or they can be any 13-bit value if the user wants a non-standard
// startup state for the GPIO.  By default, every GPIO from 5 to 37
// is set to power up as an input controlled by the management SoC.
// Users may want to redefine these so that the user project powers
// up in a state that can be used immediately without depending on
// the management SoC to run a startup program to configure the GPIOs.

`define USER_CONFIG_GPIO_5_INIT  `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_6_INIT  `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_7_INIT  `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_8_INIT  `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_9_INIT  `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_INVALID

// Configurations of GPIO 14 to 24 are used on caravel but not caravan.
`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_INVALID

`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_INVALID

`endif // __USER_DEFINES_H

Could you point me in the right direction?

Does this help?

USER_CONFIG_GPIO_5_INIT

corresponds to

mprj_io[5]

,etc.

Definitely, this makes a bit more sense now, thanks!

Let me ask ChatGPT to explain UART and I’ll get back to you…

If that’s the case, you can use

GPIO_MODE_USER_STD_INPUT

for RX and

GPIO_MODE_USER_STD_OUTPUT

.

How would I make user of the above

user_proj_example.v

? As far as I can see those are not passed into the module...

The gpio settings are external to the

user_project_wrapper

. They affect the

gpio_default_blocks

which are part of

caravel_core

block. These changes are integrated on the platform when you run the

tapeout

job.

Still unclear as to how to make use of the UART pins in

user_proj_example.v

...

You can access

io_in[5]

and `io_out[6]`/`io_oeb[6]`, right?

Ok, I was trying to confirm whether that was the way to go 🙂