hi all, /* Updated 10/15/2021: Revised using the...
# caravel
b
hi all, /* Updated 10/15/2021: Revised using the housekeeping module */ /* from housekeeping.v (refactoring a number of functions from */ /* the management SoC). */ /* is this something that i have to be worried when i trying to run the cocotb test. VCD info: dumpfile sim/uart_tx_rtl/RTL-uart_tx/RTL-uart_tx.vcd opened for output. 0.00ns INFO cocotb.regression repot_test.<locals>.wrapper_func [31mfailed[49m[39m Traceback (most recent call last): File "/home/gsb/caravel/verilog/dv/cocotb/tests/common_functions/test_functions.py", line 65, in wrapper_func await func(*args, **kwargs) File "/home/gsb/caravel/verilog/dv/cocotb/tests/uart/uart.py", line 22, in uart_tx caravelEnv,clock = await test_configure(dut,timeout_cycles=346140) File "/home/gsb/caravel/verilog/dv/cocotb/tests/common_functions/test_functions.py", line 26, in test_configure caravelEnv = caravel.Caravel_env(dut) File "/home/gsb/caravel/verilog/dv/cocotb/interfaces/caravel.py", line 49, in init self.hk_hdl = dut.uut.housekeeping File "/usr/local/lib/python3.10/dist-packages/cocotb/handle.py", line 370, in getattr raise AttributeError(f"{self._name} contains no object named {name}") AttributeError: uut contains no object named housekeeping
k
@Tim Edwards
t
I generally do not understand any details of cocotb. However, in this case, it appears that there is a reference to housekeeping as a child cell of caravel. That was the case until the most recent version of caravel (the one used from MPW-6 onward), in which an additional level of hierarchy (caravel_core) was created and the housekeeping module was moved inside of it. But the cocotb testbenches were developed for the same version of caravel, so I'm not sure why you would get such an error. I'm suspicious that some part of that test is pointing to files that predate MPW-6. I'd first check that all the files are up to date. If that doesn't reveal anything, try changing
dut.uut.housekeeping
to
dut.uut.chip_core.housekeeping
(that would be in file
verilog/dv/cocotb/interfaces/caravel.py
line 49). I can confirm that my version of the code base has
<http://self.hk|self.hk>_hdl = dut.uut.housekeeping
. If changing it doesn't solve anything (or even if it does), please track down the openlane developers or raise an issue in the caravel repository on the github issue tracker.
b
@Tim Edwards Thanks for this it works. but the problem is - the naming of the modules in the cocotb doesn't match the RTL, or the structure it is in. for example:
self.core_hdl = dut.uut.soc.core.VexriscV in cpu.py
or
dut.uut.padframe.mprj_io_in.value.binstr
in gpio.py soc/core isn't available - i am assuming it should be chip_core according to the RTL - i want to double confirm when i am trying to port to cocotb. please let me know if this is something that i can raise ticket for? thanks a lot!
t
@Bharath G S: I raised an issue on the Caravel repo and got the answer that the cocotb/ contents in the Caravel repository have been deprecated and should have been removed. The correct contents can be found in a separate repository here: https://github.com/efabless/caravel-sim-infrastructure.