Bharath G S
09/15/2023, 3:49 PMKunal
09/15/2023, 4:26 PMTim Edwards
09/15/2023, 5:25 PMdut.uut.housekeeping
to dut.uut.chip_core.housekeeping
(that would be in file verilog/dv/cocotb/interfaces/caravel.py
line 49). I can confirm that my version of the code base has <http://self.hk|self.hk>_hdl = dut.uut.housekeeping
. If changing it doesn't solve anything (or even if it does), please track down the openlane developers or raise an issue in the caravel repository on the github issue tracker.Bharath G S
09/19/2023, 5:17 PMself.core_hdl = dut.uut.soc.core.VexriscV in cpu.py
or
dut.uut.padframe.mprj_io_in.value.binstr
in gpio.py
soc/core isn't available - i am assuming it should be chip_core according to the RTL - i want to double confirm when i am trying to port to cocotb.
please let me know if this is something that i can raise ticket for?
thanks a lot!Tim Edwards
09/19/2023, 8:59 PM