Hello, I am trying to do a post implementation simulation but my design is failing the testbench. The output signals of my design are stuck at either 1 or X when using the post implementation netlist. The post synthesis netlist is behaving as expected. The design is implemented using openlane and sky130A technology (fd_sc_hd). The simulation is using the functional models of the standard cells. Does anyone have a suggestion for what could be causing this behavior? Thanks.

@Ahmad Almonaier what do you mean by

post implementation

vs

post synthesis

? Is post implementation the final gate level netlist or is it a spice netlist extracted from the layout?

Yes I meant the final Verilog gate level netlist that is generated when the openlane flow is completed. I also tried using both the powered and unpowered netlists that didn't affect the result.

Are you able to share your test scripts and netlists?

Unfortunately I'm not allowed to share these files. For more context, the design consists of several submodules that we are hardening separately. This issue can only be seen in some of the blocks. But this is still causing the entire design to not function properly.