A VHDL-based Modelling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits Sachin Maheshwari, Viv. A. Bartlett, and Izzet Kale, Member, IEEE Abstract— Adiabatic logic is an energy-efficient technique compared to conventional CMOS design. However, the time required in the design, validation and debugging increases manifold for large-scale adiabatic system designs. In this endeavor, we present a Hardware Description Language (HDL) based modelling approach for dual-rail 4-phase adiabatic logic design. The paper highlights the drawbacks of the existing approaches and proposes a new approach that A VHDL-based Modelling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits Sachin Maheshwari, Viv. A. Bartlett, and Izzet Kale, Member, IEEE Abstract— Adiabatic logic is an energy-efficient technique compared to conventional CMOS design. However, the time required in the design, validation and debugging increases manifold for large-scale adiabatic system designs. In this endeavor, we present a Hardware Description Language (HDL) based modelling approach for dual-rail 4-phase adiabatic logic design. The paper highlights the drawbacks of the existing approaches and proposes a new approach that captures the timing errors and detects the circuit’s invalid operation due to mutually exclusive inputs being violated. We develop a model library containing the function of the four periods used in the trapezoidal power-clock and the adiabatic logic gates. The validation and verification of the approach was done on the ISO-14443 standard benchmark circuit, a 16-bit Cyclic Redundancy Check circuit. The system modelled using HDL shows the timing agreement with the transistor-level SPICE simulations. The novel use of the four periods of a power-clock improves the robustness and reliability of the proposed modelling approach for the design and verification of large adiabatic circuits and systems. Index Terms—adiabatic, modelling, power-clock, timing verification, VHDLand detects the circuit’s invalid operation due to mutually exclusive inputs being violated. We develop a model library containing the function of the four periods used in the trapezoidal power-clock and the adiabatic logic gates. The validation and verification of the approach was done on the ISO-14443 standard benchmark circuit, a 16-bit Cyclic Redundancy Check circuit. The system modelled using HDL shows the timing agreement with the transistor-level SPICE simulations. The novel use of the four periods of a power-clock improves the robustness and reliability of the proposed modelling approach for the design and verification of large adiabatic circuits and systems. Index Terms—adiabatic, modelling, power-clock, timing verification, VHDL