The precheck fails and provides this output which does not give any idea of what went wrong:

[09/10/23 14:04:15 PDT] FAILED
                STDOUT: Loading Job # 14eed196-c82f-4d3d-894f-ea128a5c41e9 ...
STDOUT: Commercial Shuttle MPW Precheck | Starting Job # 14eed196-c82f-4d3d-894f-ea128a5c41e9 ...
STDOUT: {{Project Git Info}} Repository: https:/repositories.efabless.com/hadirkhan10/openram-testchip-v4.git | Branch: main | Commit: 826c56d26ac3a520fe59b37ac49f901c5e7082f9
STDOUT: {{EXTRACTING FILES}} Extracting compressed files in: openram-testchip-v4.git
STDOUT: {{Project Type Info}} digital
STDOUT: {{Project GDS Info}} user_project_wrapper: 896458b64f82e32d06cf876bc3eac33bace0c4ba
STDOUT: {{Tools Info}} KLayout: v0.28.5 | Magic: v8.3.392
STDOUT: {{PDKs Info}} SKY130A: f70d8ca46961ff92719d8870a18a076370b85f6c | Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f
STDOUT: {{START}} Precheck Started, the full log 'precheck.log' will be located in '/mnt/users_data/jobs/hadirkhan10/openram-testchip-v4/14eed196-c82f-4d3d-894f-ea128a5c41e9/logs'
STDOUT: {{PRECHECK SEQUENCE}} Precheck will run the following checks: [Makefile, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
STDOUT: {{STEP UPDATE}} Executing Check 1 of 11: Makefile
STDOUT: {{MAKEFILE CHECK PASSED}} Makefile valid.
STDOUT: {{STEP UPDATE}} Executing Check 2 of 11: Consistency
STDOUT: PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
STDOUT: COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (429666 instances).
STDOUT: MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
STDOUT: LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
STDOUT: POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
STDOUT: PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
STDOUT: {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
STDOUT: {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
STDOUT: {{STEP UPDATE}} Executing Check 3 of 11: GPIO-Defines
STDOUT: GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'openram-testchip-v4.git/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
STDOUT: GPIO-DEFINES report path: /mnt/users_data/jobs/hadirkhan10/openram-testchip-v4/14eed196-c82f-4d3d-894f-ea128a5c41e9/outputs/reports/gpio_defines.report
STDOUT: {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
STDOUT: {{STEP UPDATE}} Executing Check 4 of 11: XOR
STDOUT: {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view /mnt/users_data/jobs/hadirkhan10/openram-testchip-v4/14eed196-c82f-4d3d-894f-ea128a5c41e9/outputs/user_project_wrapper.xor.gds
STDOUT: {{XOR CHECK PASSED}} The GDS file has no XOR violations.
STDOUT: {{STEP UPDATE}} Executing Check 5 of 11: Magic DRC

How should I debug?