Im trying use given sram in a design and I'm getting following error in LVS. Please help me to figure out this.

Looks like this problem.

Thank you for replying. I tried above solutions but still error is there. Here I'm attaching the files. Please look into this and help me to remove this error.

The lvs log file still has

Circuit 2 cell sky130_sram_1kbyte_1rw1r_8x1024_8 is a black box; will not flatten Circuit 1
Warning: Equate pins:  cell sky130_sram_1kbyte_1rw1r_8x1024_8 is a placeholder, treated as a black box.

Subcircuit pins:
Circuit 1: sky130_sram_1kbyte_1rw1r_8x1024 |Circuit 2: sky130_sram_1kbyte_1rw1r_8x1024 
-------------------------------------------|-------------------------------------------
...                                  
(no matching pin)                          |wmask0                                     
wmask0[0]                                  |(no matching pin)                          
---------------------------------------------------------------------------------------

which would seem to indicate that your modified verilog is not being used (right side is verilog). Are all your modified verilog files in

openlane/adder_fsm/src

?

Yes.. File attached up there is from

openlane/adder_fsm/src

location only but still it is giving same error

Can you share your full flow output log?

This is full output log

This is the file that openlane is using for lvs

runs/first_run/tmp/signoff/37-adder_fsm.pnl.v

. Can you take a look at the sram interface there?

It is taking

net68

as input. I'm attaching file here.

Right, but the submodule terminal is

wmask0

.wmask0({net68}));

The layout terminal is

wmask0[0]