Open ChipLet(s) ... --- This repository contains the OpenChiplet specification, created for the Open Domain Specific Architecture (ODSA) sub-project within the Open Compute Project. -- ... https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2a[…]%2Fopen-chiplet&usg=AOvVaw3zPEFH0UOySVOefbYAAJWc&opi=89978449 There are currently several chiplet standards being proposed or developed, including: • Universal Chiplet Interconnect Express (UCIe): UCIe is an open standard for chiplet interconnects that is being developed by a consortium of companies including Intel, AMD, Arm, and TSMC. It is designed to be a scalable and flexible standard that can be used for a variety of applications. • Chiplet Interface Standard (CIS): CIS is a standard for chiplet interconnects that is being developed by the Chiplet Interface Working Group. It is designed to be a simpler and more lightweight standard than UCIe. • TileLink: TileLink is a standard for chiplet interconnects that is being developed by the TileLink Consortium. It is designed to be a high-performance standard that is well-suited for HPC and AI applications. • CXL: CXL is a standard for interconnecting accelerators and memory with the host processor. It can also be used to interconnect chiplets. • OpenCAPI: OpenCAPI is a standard for interconnecting accelerators and memory with the host processor. It is similar to CXL, but it is designed to be more scalable and flexible. It is still too early to say which chiplet standard will become the dominant one. However, the development of these standards is a positive sign for the future of chiplets. By providing a common set of interfaces, these standards will make it easier for chip designers to create chiplet-based systems. Slack Conversation