You received this message because you are subscribed to the Google Groups "Unum Computing" group. To unsubscribe from this group and stop receiving emails from it, send an email to unum-computing+unsubscribe@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/unum-computing/b56f2032-9fba-4742-a51d-0852bf93cc75n%40googlegroups.com. "...While currently reserved, the RISC-V V extension has encodings for Selected Element Width and Extended Memory Element Width that seem to be intended to eventually allow 128, 256, 512, and 1024-bit elements in the vector registers. As a bonus, the encoding for the extended element widths can have the lower bits be exactly the same as the width of the posits they correspond to. Combine these with the usual integer operations and most of what you need to support a quire is already available with the existing instructions. A minor kink is that currently the Zve* extensions explicitly require that each vector register be at least as wide as the widest element it supports, but given the extended element widths, that can probably be fudged. That just leaves instructions to convert to and from a quire with an extended element width, maybe even a mul_add_reduce_into_quire instruction, but that seems a bit too ambitious. If the posits themselves are stored in the vector registers as well, then the usual comparisons, negations, and shifts become available. vnclip is perfect for converting wider posits into smaller ones thanks to the Fixed-Point-Rounding Mode (vxrm) register allowing the round-to-nearest-even behavior, and the opposite direction can use vwsll, but that's only available in Zvbb rather than the usual vector extensions. Slack Conversation